Proc. of Int. Conf. on Recent Trends in Signal Processing, Image Processing and VLSI, ICrtSIV

Characterization of Low Dropout Regulator(LDO) A. Savita.C.Hiremath1, B.Nanda.B.Y2, and C. Dr. Gemson 3 1

Sambhram Institute Of Technology /Electronics & Communication, Bangalore, India Email: [email protected]

Abstract— This paper provides the characterization of LDO TPS 71148QP. LDOs (Low Dropout Regulators) are finding wide acceptance in battery-powered consumer applications for their ability to regulate the low voltages and decreased cost, size, prolonged battery life. Based on the market demand, LDO regulators offer an optimal combination of low dropout voltage, low quiescent current, fast transient response, low noise and good ripple rejection. The Characterization of an LDO includes that the LDO is tested electronically to identify its operational characteristics and these are compared with the existing datasheet values. The characterization of LDO is carried out in two phases. In the phase-I the functionality test is carried out in order to check the functionality of an LDO. In the phase –II electrical test parameters are carried out such as voltage, current and noise parameters. When the electrical test parameters match, characterization is complete and a design based on a new process can go to fabrication. Index Terms— LDO, Characterization, Quiescent Current, Dropout Voltage, PSRR, Load Regulation & Line Regulation.

I. INTRODUCTION A LDO regulator is a DC linear voltage regulator which can operate with a very small input–output differential voltage. The advantages of a low dropout voltage include a lower minimum operating voltage, higher efficiency operation and lower heat dissipation. A. Objective of the study • The datasheet of LDO TPS 7148QP is studied. • Batches of newly manufactured LDO are subjected to characterization sampling to prove that they will perform their functions with the technical characteristics for which they were designed. • Requirements are analyzed to characterize the LDO and develop the characterization methodology of LDO • Test results are compared with the specifications (datasheet values). B. Features Of TPS 7148QP The TPS7148 is a 4.85-V regulator. Designed specifically for 5-V cellular systems, and available in DIP packages . It has very low-dropout voltage (Maximum of 180 mV at Io = 500 mA) & very low Quiescent current 285μ A . The LDO TPS 7148QP provides 2% tolerance over specified conditions for fixed-Output Versions. II. BLOCK D IAGRAM OF LDO The main components are a PMOS pass Transistor and a differential amplifier (error amplifier). One input of DOI: 03.AETS.2014.5.425 © Association of Computer Electronics and Electrical Engineers, 2014

the differential amplifier monitors the fraction of the output determined by the resistor ratio of R1 and R2. The second input to the differential amplifier is from a stable voltage reference (band gap reference). If the output voltage rises too high relative to the reference voltage, the drive to the PMOS pass transistor changes to maintain a constant output voltage.

Figure 1 Block diagram of LDO

For the circuit given in the figure the output voltage is given as R1 (1) Vout = 1 +  Vref R2 LDO is characterized by its drop-out voltage, quiescent current, load regulation, line regulation, maximum current (which is decided by the size of the pass transistor), speed (how fast it can respond as the load varies), voltage variations in the output because of sudden transients in the load current, output capacitor and its equivalent series resistance. Speed is indicated by the rise time of the current at the output as it varies from 0mA load current (no load) to the maximum load current. This is basically decided by the bandwidth of the error amplifier. III. CHARACTERIZATION METHODOLOGY Characterization of an LDO can be carried out in two phases. In the Phase-I, functionality test of LDO is carried out, in order to check its functionality. The Phase-II includes, testing the different parameters of LDO. The LDO has different parameters such as voltage, current & Noise parameters. These parameters serve as the characterization guideline for testing and comparing different LDO performances. Figure 2 shows the LDO characterization methodology. The input voltage is applied to DUT using regulated power supply, included in the input circuit Bring-up. The output Voltage of DUT is measured using precision Digital Multi meter, included in the output circuit bring-up. DUT is the device under test usually LDO.

Figure 2: LDO Characterization Methodology

IV. TEST PHASES & MEASUREMENT RESULTS The TPS7148QP (LDO) can be tested at two different levels. 1. Functional Test. 2. Parameters Test. A. Functionality Test The Simple LDO regulator functionality tests will verify the low dropout regulator in its working area. The DC voltage should be applied in the given range to the low dropout regulator together with various test 122

patterns. The main goal of the test is to verify that the low dropout regulator functionalities are working correctly. The tests are used for validation & verification Of the LDO.

Figure 3 :Test Circuit For Functionality Test

Result:The input voltage is varied from 5.5V to 10V,gives an regulated output voltage 4.8358V.From this test conclude that ,the functionality of the LDO TPS7148 is according to the specifications. B. Parameters Test The parameters serve as the characterization guideline for testing and comparing different LDO performances. The test parameters LDO are namely : Voltage parameters, Current and , Noise Parameters. C. Voltage Parameters Dropout Voltage:Dropout voltage is defined as the minimum input-to-output voltage different where output voltage of the LDO linear regulators remains regulated.

Figure 4: Test Circuit Of Dropout Voltage

Figure 5: Dropout Region of LDO TPS7148

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The working region for LDO is the “regulation region”, where it can provide a steady output voltage, in a wide range of load current. In the dropout region, the PMOS pass element is simply a resistor, and dropout is expressed in terms of its on-resistance (Ron). Vdropout = Io .Ron (2) Figure 5 shows the input/output characteristics of the LDO TPS7148 regulator. The dropout voltage of the TPS7148 is typically 6 mV at 10 mA. Thus, the LDO regulator begins dropping out at 4.75V input voltage; the range of the dropout region is between approximately 4.75-V and 5.5 input voltage. Below this, the device is nonfunctional. Low dropout voltage is necessary to maximize the regulator efficiency. D. Line Regulation Line regulation is a measure of a system's ability to regulate the output voltage under a varying input voltage. Line regulation is defined as: Line Regulation = ∆Vout / ∆Vin (3) Figure 6 shows the input voltage transient response of the TPS7148 LDO regulator. A step change of input voltage was applied to the regulator, which is shown at the lower left in the figure. The resultant output voltage has been changed due to the different input voltages as shown in the right side of the figure.

Figure 6 : Line Transient Response

The line regulation is determined by ∆VLR1 and ∆VLR2 since line regulation is a steady-state parameter (i.e., all frequency components are neglected).

Figure 7: Performance of TPS7148 LDO with respect to the input voltages

Figure 7 shows the circuit performance of the TPS7148 LDO regulator with respect to the input voltages. The broken line shows the range of the output voltage variation (∆VLR) resulting from the input voltage change. Increasing open loop gain improves the line regulation. E. Load Regulation Load regulation is a measure of system's ability to regulate the output voltage under a varying load condition. Load regulation is defined as: Load Regulation = ∆Vout / ∆I0 (4) 124

The worst case of the output voltage variations occurs as the load current transitions from zero to its maximum rated value or vice versa, which is illustrated in Figure 8. The load regulation is determined by the ∆VLDR since load regulation is a steady-state parameter like the line regulation. The TPS7418 LDO regulator gives 60 mV load regulation.

Figure 8: Load Transient Response

F. Current Parameters Quiescent Current: Quiescent, or ground current, is the difference between input and output currents. Low quiescent current is necessary to maximize the current efficiency. Figure 9 shows the quiescent current that is defined by IQ = Iin - Iout. (5)

Figure 9: Test Circuit For Quiescent Current

The quiescent current, also known as ground current or supply current, which accounts for the difference, although small, between the input and output currents of the LDO. The LDO TPS 7148 has very low quiescent current of 285μA. Quiescent current is current drawn by the LDO in order to control its internal circuitry for proper operation. The series pass element, topologies, and ambient temperature are the primary contributors to quiescent current. Many applications don't require an LDO to be in full operation all of the time (i.e. supplying current to the load). In this idle state the LDO still draws small amounts of quiescent current in order keep the internal circuitry ready in case the load is enabled. When no current is being supplied to the load, can be found as follows: PLOSS = VIN .IQ (6) In order to minimize power loss while the LDO is idle, quiescent current should be as low as possible. Decreased power consumption allows portable applications to achieve longer battery life. It's also beneficial for enclosed applications that have trouble dissipating heat that may result from inefficient LDOs. G. Noise Parameter Power Supply Rejection Ratio(PSRR):Power supply rejection ratio, or PSRR, refers to the LDO's ability to reject ripple it sees at its input. As part of its regulation, the error amplifier and band gap attenuate any spikes 125

in the input voltage that deviate from the internal reference to which it is compared. In an ideal LDO, the output voltage would be solely composed of the DC frequency. However, the error amplifier is limited in its ability to gain small spikes at high frequencies. PSRR is expressed as follows:     = 20  (7)    Power supply rejection ratio (PSRR), also known as ripple rejection, measures the LDO regulator’s ability to prevent the regulated output voltage fluctuating caused by input voltage variations. The same relation for line regulation applies to PSRR except that the whole frequency spectrum is considered. The 7148QP LDO has PSRR of 45.57 dB at 100Hz with Ripple Input190mV & Ripple Output 1mV.

Figure 10 : Power Supply Rejection Ratio

Figure 11: Ripple Input/output Waveforms

H. Efficiency and Heat Dissipation One of the advantages of having a low drop-out voltage is the ability to limit power dissipation and achieve higher efficiency. The power dissipated by a typical LDO is calculated as follows: PLOSS = (VIN-VOUT).IOUT + (VIN.IQ) (8) Therefore, one can calculate the efficiency as follows: (9)

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where

.

However, when the LDO is in full operation (i.e. supplying current to the load) we see that:

. This allows us to reduce

to the following:

(10) which further reduces the efficiency equation to: η = VOUT/ VIN (11) In full operation, it is shown that the efficiency of an LDO is enhanced by minimizing the difference between Vin and Vout. The lower the drop-out specification for a particular LDO, the smaller this differential can be. It is important to keep thermal considerations in mind when using a low drop-out linear regulator. Having too wide a differential between input and output voltage could lead to large power dissipation. Depending on the package, excessive power dissipation could damage the LDO and/or cause it to go into thermal shutdown. V. EXPERIMENTAL SETUP & RESULTS: The LDO TPS 7148QP regulator test circuits can be developed & tested the different parameters of LDO. LDO TPS 7148QP characterization results for the experimental functionality test & parameters tests are obtained. The functionality of the LDO TPS 7148QP is according to the specifications ,it gives regulated output 4.85V under input voltage Vin from 5.5V to 10V.

Figure 12: Experimental Test Setup

In parameters test, dropout voltage measurement is according to the specifications & is operated with minimum dropout voltage of 181.7 mV under max load condition. Quiescent current is according to the specifications under no load condition of max 9.9826mA. The line regulation values according to the specifications under different test conditions & gives 27mv regulations under input voltage 5.5V to 10V. The line regulation is required to maintain the regulated output voltage with changes in the input voltage. This measurement is normally taken under conditions of low power dissipation to reduce the effect of average chip temperature. The obtained line regulation values are according to the specification. The load regulation values according to the specifications under different test conditions & gives 42mv regulations under input voltage 5.85V to 10V.The Noise parameter PSRR is according to the specifications & gives 53dB at input frequency 120Hz,Io=50μA.The load regulation is required to maintain the regulated output voltage with changes in the load condition. VI. CONCLUSION LDOs are low dropout, low quiescent current less expensive & available in small sizes. As a result LDO can be used in portable battery operated products to achieve power management.

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Batches of newly LDO’s are subjected to characterization to prove that they will perform their functions with the technical characteristics for which they were designed. The different test circuits can be developed & tested. In the Characterization first step is to test the functionality of the LDO TPS 7148QP is according the specifications. The second step is to Characterize the different Voltage, current noise parameters of the LDO. As well as the operation philosophy and the design procedure here presented can be applied for characterization of other kind of DUTs. ACKNOWLEDGMENT We the authors of this paper would like to grateful acknowledge with thanks to SAIT,Management Bangalore, for providing us the infrastructure and giving us an opportunity to carry out the work. We are very grateful to our Principal SAIT Bangalore, for his kind cooperation and moral support through out this work. We express our gratitude to HOD ECE department SAIT, Bangalore for his constant encouragement valuable timely advise. REFERENCES [1] Xiao fan Qiu, “Analysis and Characterization of a programmable Low-dropout regulator”, Texas A&M University, April 2007, pp. 1-10. [2] M. Kay, "Design and Analysis of an LDO Voltage Regulator with a PMOS Power Device," Preliminary paper publication, Texas Instruments [3] John C. Teel, “Understanding power supply ripple rejection in linear regulators”, Texas Instruments Incorporated, 2005, pp.1-4. [4] Glenn Morita, “Noise Sources in Low Dropout (LDO) Regulators”, One Technology Way, May 2011, pp.1-12. [5] K.M. Tham and K. Nagaraj, "A Low Supply Voltage High PSRR Voltage Reference in CMOS Process," IEEE Journal of Solid-State Circuits, vol.30 #5 , May 1995.pp. 586-590. [6] F. Goodenough, "Low Dropout Linear Regulators," Electronic Design , pp. 65-77, May 1996. [7] Robert Jon Milliken, “ Low drop-out voltage regulator with fast transient response”, August 2000, pp.4-15.

AUTHORS PROFILE Ms. Savita. C. Hiremath. Currently working as a Lecturer in Electronics and communication department at Sambhram Institute of Technology, Bangalore. Specialization: VLSI DESIGN & TESTING. Ms. Nanda. B. Y Currently working as a Lecturer in Electronics and communication, department at Sambhram Institute of Technology, Bangalore. Specialization: VLSI DESIGN & EMBEDDED SYSTEMS. Dr. Gemson. Currently working as a Professor in Electronics and communication department at Sambhram Institute of Technology Bangalore

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