Chapter 4 Part 1 Sequential Circuits

Overview of Chapter 4 University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 § ...
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Overview of Chapter 4

University of Wisconsin - Madison

ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu

Spring 2002

§ Part 1:

• •

Logic and Computer Design Fundamentals

Types of Sequential Circuits Storage Elements § Latches and Flip-Flops

§ Part 2:



Chapter 4 – Part 1

Sequential Circuit Analysis § State Tables and State Diagrams

§ Part 3:

Sequential Circuits



Sequential Circuit Design § Specification § Assignment of State Codes § Implementation

Originals by: Charles R. Kime and Tom Kamisnski

§ Part 4:

Modified for course use by: Kewal K. Saluja and Yu Hen Hu



HDL Representation

© 2001 Prentice Hall, Inc Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Sequential Circuits

2

Sequential Circuits Inputs

Combina tional Logic

Storage § A Sequential circuit contains: Elements

• Combinatorial Logic:

Chapter 4-1

State

§ Implements a multiple-output switching function § Inputs are signals from the outside world. § Outputs are signals to the outside world. § Other inputs, State or Present State , are signals from storage elements. § The remaining outputs, Next State are inputs to storage elements.

Outputs

Inputs Storage Elements • Combinatorial Logic: § Next state function : Next State = f(Inputs, State) § Output function (Mealy): Outputs = g(Inputs, State) § Alternate output function (Moore): Outputs = h(State) • Type of output function heavily influences the design

Next State

Combina tional Logic State

Outputs

Next State

• Storage elements: Latches or Flip-Flops Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 4-1

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Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 4-1

Types of Sequential Circuits

Discrete Event Simulation

§ Depends on time at which inputs are observed by storage elements and state of storage elements change § Synchronous

§ In order to understand the time behavior of a Sequential Circuit we use discrete event simulation. § Rules:

• •

Behavior defined from knowledge of its signals at discrete instances of time Storage elements affected by inputs and can change state only in relation to a timing signal (clock pulses from a clock)

• Gates modeled by an ideal (instantaneous) function and a fixed gate delay

§ Asynchronous

• •

• Any change in input values is evaluated to see if it

Behavior defined from knowledge of inputs at any instant of time and the order (in continuous time) in which inputs change If clock just regarded as another input, all circuits are asynchronous!

causes a change in output value

• Changes in output values are scheduled for after the fixed gate delay

• At the time for a scheduled output change, the

§ Synchronous abstraction makes complex designs tractable! Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 4-1

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output value is changed along with any signals/lines connected to it 5

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

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1

Simulated NAND Gate

Gate Models

§ Example: A 2 -Input NAND gate with a 5 ns. delay:

§ Suppose we represent gates with delay n ns as follows:

F(Instantaneous) A F

DELAY 5 ns.

B

§ Assume A and B have been 1 for a long time § At time t=0, A changes to a 0 at t=8 ns, back to 1.

n

n

n

t (ns) A B F(I) F Comment –∞ 1 1 0 0 A=B=1 for a long time 0 F(I) changes to 1 1⇒ 0 1 1⇐0 0 0 1 1 1⇐0 F changes to 1 after a 5 ns delay 5 8 1⇐0 1 1⇒0 1 F(Instantaneous) changes to 0 13 1 1 0 1⇒0 F changes to 0 after a 5 ns delay Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

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Storing State

0

0.1 0.1

§ The circuit becomes: § With function:

Y

Y(t – 2) for S = 0

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0.1

Y

0.1

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

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Storing State (Continued)

§ Simulation example as input signals change with time. Changes occur every 100 ns, so that the 0.2 ns delays are negligible.

§ Suppose we 0.1 place an inverter in 0 in the “feedback 0.1 S path.” 0.1 B § The following behavior results: Comment B S Y § The circuit is 0 1 0 Y = B when S = 1 said to be 1 1 1 unstable. 1 0 1 Now Y "remembers" B 1 0 0 Y at 0.2 ns later § For S = 0 it is an 1 0 1 Y a t 0.2 ns later oscillator! 1 0 0 Y at 0.2 ns later

Comment Y = B when S = 1 Now Y “remembers” B for S = 0 even after B changes

Y = B when S = 1 Y “remembers” B for S =0 even after B changes

§ Y represent the state of the circuit, not just an output. Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

0.1

B S Y § The simple combinational circuit has now become a sequential circuit because its output is a function of a time sequence of input signals!

Storing State (Continued)

Y 0 1 1 1 1 1 0 0 0 0

0

• Y = B for S = 1, and S • Y(t) dependent on B

0.1

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

S 1 1 0 0 0 0 1 0 0 0

8

Storing State (Continued)

A B S Y § What would happen if we connect output signal Y to input signal A?

B 0 1 1 0 1 0 0 0 1 0

Chapter 4-1

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Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 4-1

0

§ Consider a simple A 2-input multiplexer: § With function: • Y = A for S = 1 S • Y = B for S = 0 B

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Y

12

2

Basic (NAND) S –R Latch § “Cross-Coupling” two NAND gates gives theS -R Latch:

Basic (NOR) S – R Latch

S (set)

Q'

R (reset)

§ Which has the time sequence behavior:

R 1 1 1 0 1 0 1

S 1 0 1 1 1 0 1

Q ? 1 1 0 0 1 ?

§ Cross-coupling two NOR gates gives the S – R Latch: § Which has the time sequence R S behavior: 0 0

Q

Q' ? 0 0 1 1 1 ?

Comment We don't know "Set" Q to 1 Now Q "remembers" 1 "Reset" Q to 0 Now Q "remembers" 0 Both go high INSTABILITY

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 4-1

0 0 1 0 1 0 13

1 0 0 0 1 0

R (reset)

Q

Q'

S (set)

Q ? 1 1 0 0 0 ?

Q' ? 0 0 1 1 0 ?

Comment We don't know "Set" Q to 1 Now Q "remembers" 1 "Reset" Q to 0 Now Q "remembers" 0 Both go low INSTABILITY

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

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Clocked (or Gated) S - R Latch Clocked S - R Latch (Continued) Adding two NAND gates to the basic S - R NAND Latch, we arrive at the Clocked S – R Latch:

S

The Clocked S-R Latch can be described by a table:

Q

Q C

Q'

Q'

R

R

This has a time sequence behavior similar to the Basic S -R Latch except that: • S and R are now active high signals (i.e. -- a "1" signal on S sets Q to 1) and • The S and R inputs are only observed when the line C is high. • C has the meaning "Clock" or "Clock Pulse". Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 4-1

The table describes what happens after the clock [at time (t+1)] based on:

15

Q(t+1)

0 0 1 1 0

0 1 0 1 0

0 0 1 ??? 1

Comment No change Clear Q Set Q Indeterminate No change

1 1 1

0 1 1

1 0 1

0 1 ???

Clear Q Set Q Indeterminate

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 4-1

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D Latch S

We can describe the behavior of output Q at time (t+1) (immediately after one clock pulse) using a K-Map:

R

0 0 0 0 1

current inputs (S,R) and current state Q(t).

Characteristic Equation for S - R Latch

0

Q

1

4

1

5

X X

3

7

1 1

Adding an inverter to the S-R Latch, gives the D Latch:

2

R

The Clocked S – R Latch has the symbol:

S

D Q C

6

Q'

Note that there are no "Indeterminate" states!

R

We can see that: Q(t+1) = S + R'⋅ Q given that (both are not high at once): S⋅ R = 0

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Q(t) S

S

C

§Q §0 §0 §1 §1

Q

C Q' Chapter 4-1

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§D §Q(t+1) §Comment §0 §0 §No change §1 §1 §Set Q §0 §0 §Clear Q §1 §1 §No Change

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

The graphic symbol for a D Latch is: D

Q

C

Q'

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3

Latch and Flip-Flop Triggering So far, the latches we have talked about are "clocked" with an input pulse. Here are some possible wave forms: Clock Period



Positive Clock Pulse



Negative Clock Pulse W = Pulse Width Clock Period = Time between referenced edges. Reference level is generally 50%. Rise and Fall times may be important as well.



Positive Clock Pulse



w

1 0



Positive edge

Negative Edge

1



0 Clock Period Negative Clock Pulse

w

System Level Clocking

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 4-1

Consider a system comprised of ranks of latches or flipflops connected by logic:

If the Clock Period is TOO SHORT, some data changes will not propagate through the network. If the Clock Pulse Width is TOO LONG, some data will propagate through the second rank of latches! 19

Master-Slave Flip-Flop

One way to solve the Clocking Problem is with a master-slave organization:

D Q

D Q

C Q'

C Q'

D Q

D Q

C Q'

C Q'

D Q

D Q

C Q'

C Q'

D Q

D Q

C Q'

C Q'

D Q

D Q

C Q'

C Q'

CLOCK

CLOCK

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 4-1

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Edge Triggered Flip-Flops

R

R

C

C

S

S

Q

R

Edge triggered Flip-Flops are sensitive to a small window for data changes around the time of a clock edge. • Setup Time: The time required for input data to be stable before the clock edge. • Hold Time: The time data must remain stable after the clock edge.

Q

Q

C Q'

S

Q'

Q'

§The complement of the clock is used to change the outputs. §Now outputs change on C only. §Problem: One's catching in Master can result into instabiltiy.

D

Q

T

Q

J

Q

C C

Q'

C

Q'

Q'

K

Positive Edge Triggered FFs D

Q

T

Q

J

Q

C C

Q'

C

Q'

K

Q'

Negative Edge Triggered FFs

§Another solution: Use D-FF's or §Edge Triggering

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 4-1

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Flip-Flop Characteristic Tables

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Characteristic Tables

The Characteristic Tables: Clocking conditions are: • Show current inputs. • Positive level triggered. • Show current state implicitly. • Negative level triggered. • Positive edge triggered. • Predict flip-flop state AFTER CLOCKING. • Negative edge triggered. NOTE: Proper clocking or flip-flop operation may be subject to conditions such as: • Set-up and hold times are met. • Simultaneous SR changes disallowed. Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 4-1

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J K Q(t+1) Comment

§S §R §Q(t+1) §Comment

0 0

Q(t)

No change

0 1 1 0 1 1

0 1 Q'(t)

Clear Q Set Q Complement Q

§0 §0 §1 §1

T

Q(t+1)

0 1

Q(t) Q'(t)

§0 §1 §0 §1

§Q(t) §0 §1 §???

Comment

D

Q(t+1)

No change Complement Q

0 1

0 1

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

§No change §Clear Q §Set Q §Indeterminate Comment Clear Q Set Q

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4

J-K Master Slave Flip Flop

Master Slave Symbols Master

Two SR Latches driven by inverted clocks form a master-slave configuration. J Input logic forms the JK logic K transition: • Set (master) = J•Qs' • Reset (master) = K• Qs

Slave

Master-Slave Flip Flops are denoted by a line near the outputs.

Qm S C R

Q

S Q C R Q

Q

Qs

This highlights the fact that the slave changes AFTER the master clocking condition is deasserted.

CP

SR S

R

25

Flip-Flop Conventions

B

B

A Q

C

K

Q'

Q

C

R Q'

K Q'

Negative Pulse Triggered Master/Slave FFs

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 4-1

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TPHL: Propagation time high-to-low -- the time required for an output to transition from a high logic level to a low logic level from an input event (usually clock). Clock Skew: Difference in clock arrival times at different flip-flops.

C Q

Q

Q

C Q

Q' Q

Tsu : Set-up time: Time data must be stable at FFs before the clock. Minimum clock period is set by:

C Q

MAX(TPHL,TPLH) + LogicDelay + Tsu Hold Time and Clock Skew constrain the minimum logic plus flipflop delay.

Q

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 4-1

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Calculating Clock Frequency A

Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Chapter 4-1

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Calculating Clock Frequency (Continued) B

C

D

DQ CQ'

Given the network below, assume signal A is changing from "0" to "1":

DQ CQ'

CLOCK

CLOCK

A

B

C

D

D Q C Q'

DQ C Q'

CLOCK

CLOCK Clock Period

Clock Period

Clock Period = t PLH(Flip-Flop) +3*t PLH(Logic) + t s u (Flip-Flop

CLOCK tpHL (Flip-Flop) A tpHL (Logic)

Frequency = 1/(Clock Period)

B tpHL (Logic) C

CLOCK tpLH (Flip-Flop) A tpLH (Logic) B tpL H(Logic) C tpLH (Logic)

tpHL (Logic)

We ususally pick MAX(t PHL, TPLH).

D tsu (Flip-Flop) Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Q'

C

TPLH: Propagation time low-to-high -- the time required for an output to transition from a low logic level to a high logic level from an input event (usually clock).

A

C

Frequency = 1/(Clock Period)

C

JK J

Logic gate, Latch and Flip-Flop timing parameters:

CK C

CK

Clock Period = t PHL(Flip-Flop) +3*tPHL(Logic) + tsu (Flip-Flop)

S Q

Propagation Delay

Q

Given the network below, assume signal A is changing from "1" to "0":

SR

Q

Positive Pulse Triggered Master/Slave FFs

Chapter 4-1

A Bubble near a clock input denotes an active low assertion. A Triangle near the clock input denotes edge sensitive. A L-Shaped Line near the output denotes Master/Slave.

JK J

C

Master Set is possible if the slave Qs is currently "0" any time the clock CP is high ! Master Reset is possible if the slave Qs is currently "1" any time the clock CP is high! This is referred to as One's Catching. Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

Q

Chapter 4-1

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Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc

D tsu (Flip-Flop)

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5

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