Chapter 13 Asynchronous Sequential Network _____________________________________________ 13.0 Introduction Asynchronous sequential circuit is specified by a timing sequence of inputs, outputs, and internal states. The change of internal state occurs in response to the synchronized clock pulse. Asynchronous sequential circuit does not use clock pulses. The memory element of the circuit is unclocking flipflop or timedelay elements. The block diagram of an asynchronous sequential circuit is shown in Fig. 13.1.
Figure 13.1: The block diagram of an asynchronous sequential circuit
The feedback would not have immediate response because of the propagation delay in the combinational circuit. After this time lapse, the output will only respond. Owing to the delay, there is unstable state associated with, race issue, and hazard issue, which shall be dealt with. Asynchronous sequential circuit is faster and more difficult to design than synchronous sequential circuit. Asynchronous sequential circuit does not use clock pulses. The change of internal state occurs when there is a change in the input variables. The circuit is more difficult to design because of the timing problem involved in the feedback path.  163 
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Asynchronous sequential circuit is useful in a variety of application especially for the case where speed of operation is important. In the application where input signal can be changed at any time such as the communication between two units, the design must be done with asynchronous circuits. The circuit is also less expensive to design because there is no requirement to design the clock pulse generation circuit.
13.1 Analysis Procedure The analysis of asynchronous sequential circuits consists of obtaining a table or diagram that describes the sequence of internal states and outputs as a function of changes in the input variables. The analysis covers obtaining the transition table, flow table, race condition, and stability considerations.
13.1.1 Transition Table The procedure for obtaining a transition table from an asynchronous circuit is as follow. • Determine all feedback loops in the circuit. • Designate the output of each feedback loop with variable Yi and its corresponding input with yi for i = 1, 2,….., k, where k is the number of feedback loops in the circuit. • Derive the Boolean functions of all Y’s as a function of the external inputs and the y’s. • Plot each Y function in a map using y variables for the row and the external inputs for the column. • Combine all maps into one table showing the values of Y = Y1Y2…Yk inside each square. • Once the transition is ready, the behavior of the circuit can be analyzed by observation for the state transition as a function of changes in the input variables. Consider an asynchronous circuit shown in Fig. 13.1, the Boolean functions of the output Y1 and Y2 are respectively equal to Y1 = x ⋅ y1 + x ⋅ y 2
(13.1)
Y2 = x ⋅ y1 + x ⋅ y 2
(13.2)  164 
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Figure 13.1: An asynchronous sequential circuit
The transition tables are shown in Fig. 13.2. x y1y2 00 01 11 10
0
1
0 1 1 0
0 0 1 1
x y1y2 00 01 11 10
0
1
0 1 1 0
1 1 0 0
x y1y2 00 01 11 10
0
1
00 11 11 00
01 01 10 10
(a) Map for Y1 = x ⋅ y1 + x ⋅ y 2 (b) Map for Y2 = x ⋅ y1 + x ⋅ y 2 (c) Transition table Figure 13.2: Map and transition table of the circuit shown in Fig. 13.1
The transition table shown in Fig. 13.2(c) the value of Y=Y1Y2. The circled transitions are stable transition since the input y1y2 is the same. The non circled transition is not stable the output is not same as y1y2. The change of input from =y1y2x = 000 to y1y2x = 001 will yield output Y = 01, which is not 00. Thus, this transition is not stable. The state table for the circuit is shown in Fig. 13.3. Present State 0 0 1 1
Next State x=0 0 1 1 0
0 1 0 1
x=1 0 1 0 1
0 0 1 1
Figure 13.3: State table for circuit shown in Fig. 13.1  165 
1 1 0 0
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13.1.2 Flow Table During the design of asynchronous sequential circuit, it is more convenient to name the states by letter symbols without making specific reference to their binary values. Thus, using this approach the flow table of Fig. 13.2(c) is shown in Fig. 13.4 after assign 00 = a, 01 = b. 11 = c, 10 = d. x y1y2 a b c d
0
1
a c c a
b b d d
Figure 13.4: Flow table shown in letter symbol
Consider a twostate with two inputs and one output flow table shown in Fig. 13.5. The states shown in red color are the stable state. x1,x2
00
01
11
10
a
a, 0
a, 0
a, 0
b
a, 0
a, 0
b, 1
b, 0 b, 0
y
Figure 13.5: A twostate with two inputs and one output flow table
The transition table and the map of the output are shown in Fig. 13.6. x1,x2 y a b
00
01
11
10
0 0
0 0
0 1
1 1
x1,x2 y 0 1
00
01
11
10
0 0
0 0
0 1
0 0
(a) Transition table for Y = x 1 ⋅ x 2 + x 1 ⋅ y (b) Map for z = x1 ⋅ x 2 ⋅ y Figure 13.6: The transition table and map of the output of flow table shown in Fig. 13.5
The circuit of the design based on the transition table and map shown in Fig. 13.7.
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Figure 13.7: Circuit design based on the transition table and map shown in Fig. 13.6
13.1.3 Race Condition A race condition is said to be exist in asynchronous sequential circuit when two or more binary state variables change value in response to change in an input variable. When unequal delays are encountered, a race condition may cause the state variables to change in an unpredictable manner. For an example state variables change from 00 to 11, due to the difference in delay, the change may take place in two sequences. If the first variable changes faster than the second variable then the sequence is from 00→10→11. If the second variable changes faster than the first one then the sequence is 00→01→11. If the final state does not depend on the sequence taken place then the race is called a noncritical race. If it is possible to end with more than one state depending on the order of the state change then it is a critical race, which must be avoided. The transition table shown in Fig. 13.8 is a noncritical type. x y1y2 00 01 11 10
0
1
00
11 11 11 11
Figure 13.8: A noncritical race transition
If the initial state is y1y2x = 000, by changing the external input from x = 0 to 1, the state will change to 111. Depending on the delay, the sequence of transition can be from 00→11, 00→01→11 or 00→10→11.  167 
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The transition table shown in Fig. 13.9 illustrates race condition. We start with state y1y2x = 000 and change the state to y1y2x = 001. It would mean the final state that would like to be is y1y2 = 11. Depending on the delay time, it can end with different state. If first variable is responding faster than the second variable, the state will end with y1y2 = 10, which is a stable state. If second variable is responding faster than the first variable, the state will end with y1y2 = 01, which is also a stable state. If both first and second variables respond simultaneously the state will end with y1y2 = 11, which is also a stable state. The conclusion means that the race condition can cause the final state to be ended with three possible states. x y1y2 00 01 11 10
0
1
00
11 01 11 10
Figure 13.9: A critical race transition
Race condition can be dealt with by proper binary assignment to the state variable. The state variables must be assigned binary number in such a way that only one state variable can be change at any one time when a state transition occurs in the flow table. We shall discuss the method in Section 13.5. Figure 13.10 shows a cycle transition. We start with state y1y2x = 000 and change the state to y1y2x = 001. The state is a cycle transition from 00→01→11→10.
x y1y2 00 01 11 10
0
1
00
01 11 10 01
Figure 13.10 A cycle transition
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13.1.4 Stability Consideration Owing to the feedback connection that exists in synchronous sequential circuits, care must be taken to ensure that circuit does not become unstable. An unstable condition will cause the circuit to oscillate between unstable states. The transition table method of analysis can be useful in detecting the occurrence of instability. An unstable circuit is shown in Fig. 13.11. This circuit has function Y = X1 ⋅ X 2 + X 2 ⋅ y .
Figure 13.11: An unstable logic circuit
The transition table is shown in Fig. 13.12. The cycled values are value that Y = y. The uncycled values represent unstable state. Example of the unstable stable is when yx1x2 = 111 which should yield y = 0. x1x2 y 0 1
00
01
11
10
0 0
1 1
1 0
0 0
Figure 13.12: The transition table of circuit shown in Fig. 13.11
13.2 Analysis of Asynchronous Circuits The most common asynchronous circuit is the SR flipflop shown in Fig. 13.13.
Figure 13.13: A SR flipflop  169 
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If the SR flipflop is redrawn according to the model shown in Fig. 13.13 i.e. including the propagation delay, the SR flipflop shall be as shown in Fig. 13.14.
Figure 13.14: The model of an SR flipflop with delay
The output Y is not immediately soon after the input y change because there is a propagation delay between two NOR gates. The Boolean function of output Y is Y = S + y + R = (S + y) • R
(13.3)
Based on equation (13.4), the flow table of the flipflop is derived and shown in Fig. 13.15. Next State Present Output SR Value State 00 01 10 11 y Y Q 1 0 0 1 0 0 1 Figure 13.15: The flow table of SR flipflop
Those next state values that marked in cycle are stable state. If the state y = 0 is assigned as A and y = 1 is assigned as B then the state assignment table of the SR flipflop is shown in Fig. 13.16. Present State y A B
Next State 00
SR Value 01 10 Y B A
Output 11
A
Figure 13.16: State assignment table of SR flipflop  170 
Q 0 1
13 Asynchronous Sequential Network
At y = 0 state, changing SR value 11 to 10 will cause Y = B. After the propagation delay, the input shall be ySR = 110, in which the output Y shall be settled at B. At y =1 state, changing SR value from 10 to 11 will cause Y = A. After the propagation delay, the input shall be ySR = 011. Based on the flow table, the flow diagram of SR flipflip is shown in Fig. 13.17.
Figure 13.17: The flow diagram of SR flipflop
Based on the results of state table shown in Fig. 13.16, the Mealy model flow diagram is shown in Fig. 13.18.
Figure 13.18: Mealy model flow diagram of SR flipflop
Let’s look at a gated D flipflop shown in Fig. 13.18. The Boolean function of the output Y is Y = (C • D) • ((C • D) • y) = CD + C • y + D • y = CD + C • y , after delete the redundant D•y that solve race condition known as hazard that will be dealt later on. Two gatedD flipflop is used to implement the masterslave D flipflop. Thus, its circuit diagram is shown in Fig. 13.20.
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Figure 13.19: D flipflop
Figure 13.20: A masterslave D flipflop
Boolean function of the masterslave D flipflop shall be Ym = C•D + C • y m
(13.4)
Ys = C • y m + C • y s
(13.5)
and
The flow table of masterslave D flipflop is shown in Fig. 13.21. Present State ymys 00 01 10 11
00
00 11
Next State CD Value 01 10 YmYs
Output 11 10 11
00 11
00 01
Figure 13.21: The flow table of masterslave D flipflop  172 
Q 0 1 0 1
13 Asynchronous Sequential Network
If state assignment is made such that S1 = 00, S2 = 01, S3 = 10, and S4 = 11, the state assignment table including the unspecified entries shown as “” shown in Fig. 13.22. Present State ymys S1 S2 S3 S4
00
S1 
Next State CD Value 01 10 YmYs
Output 11 S3 S4
S4
S1 S2
Q 0 1 0 1
Figure 13.22: State assignment table including unspecified entries of masterslave D flipflop
The unspecified entries are derived based on the fact that the input must change one at a time. Thus, the input changes from CD = 10 to CD = 01 for ymys = 01 is unspecified. Similarly, the input changes from CD = 11 to CD = 01 for ymys = 10 is unspecified.
13.3 Designing Asynchronous Network Circuits The way to design the asynchronous network circuit is same as how the synchronous network circuit is designed. The procedure listed below shall be used when designing the asynchronous network circuit. • Devise a state diagram for an FSM that realizes the required functional behavior. • Derive the flow table and reduce the number of possible state. • Perform the state assignment and derive the excitation table. • Obtain the next state and output expressions. • Construct a circuit that implements these expressions. Let’s use the design of an arbiter illustration. An arbiter is a hardware that would decide the request from the digital system to utilize the shared resource such as a printer connected to two computer systems. If there is a request from computer 1 to use the printer, the arbiter will process the request and acknowledge the request if the printer is free. If the printer is busy printing the computer 2’s request, then the arbiter would not assign the printer to computer 1 until printer has printed computer 2’s request and computer 2 returns the end of  173 
13 Asynchronous Sequential Network
print signal to the arbiter. The flow diagram of the arbiter is shown in Fig. 13.23.
Figure 13.23: The flow diagram of an arbiter
r1r2 = 00 shall mean there is no request. r1r2 = 01 shall mean B is requesting and r1r2 = 10 shall mean C is requesting. Output g2g1 are the acknowledged codes of the arbiter. The state assignment table of the arbiter is shown in Fig. 13.24. Present State y2y1 A B C D
00
A A 
Next State r1r2 Value 01 10 Y2Y1 B C C B B C
Output 11 

g1g2 00 11 10 dd
Figure 13.24: The state assignment table of the arbiter
For circuit stabilized at B, changing from r2r1 from 11 to 10 should end with Y2Y1 = C, which is also meant that the value of y2y1 should be changing to 10. If y2 changes faster y1, then y2y1 should be 11, which is the D state. Since D state has value Y2Y1 is 10, it will move to the stable C state. If y1 changes faster than y2, y2y1 shall end with 00 state, which is a stable A state. Thus, there is race issue here, which is a critical race since its final state depends on propagation delay. Similarly, from stable C state change r1r2 from 11 to 01 will have the  174 
13 Asynchronous Sequential Network
same race issue like the earlier case. In order to avoid these critical races, one needs to change the states to state A marked in red to avoiding critical racing. The modified state assignment table is shown in Fig. 13.25. Present State y2y1 A B C D
00
A A 
Next State r1r2 Value 01 10 Y2Y1 B C A A B C
Output 11 

g1g2 00 11 10 dd
Figure 13.25: State assignment table of an arbiter after avoiding critical race
The next state Boolean function for Y1 and Y2 are Y1 = r1 • y 2 and Y2 = r1 • r2 • y1 + r2 • y 2 . The logic circuit of the arbiter is shown in Fig. 13.26. This circuit is simpler than the circuit designed with flipflop and clock pulse circuitry. The circuit can respond almost instantly and does not wait for clocking pulse to respond like the case where it is designed using synchronous approach.
Figure 13.26: The logic circuit of an arbiter
13.4 State Reduction The procedure for reducing the number of internal states in an asynchronous sequential network resembles the procedure that used for synchronous network  175 
13 Asynchronous Sequential Network
circuit. Equivalency pair, implication chart, state assignment, and merging of flow table are some of the methods used for state reduction. Equivalency pair, implication chart, and state assignment methods have been discussed in detail in Chapter 11. Thus, the procedure shall not be repeated here. Only the merging of flow table method shall be discussed. The procedure of merging of state table method is as follows: • Determine all equivalency pairs by using the implication chart or other methods such as equivalency pairs. • Find the maximal equivalency using merger diagram. • Find a minimal collection of equivalency that covers all states and closed. The minimal collection of equivalencies is used to merge the row of the state table. Let’s use the design of gated D flipflop illustrated in Fig. 13.19 as an example. The state table of the D flipflop is shown in Fig. 13.27. It is derived based on Boolean function Y = (C • D) • ((C • D) • y) = CD + C • y + D • y . The flow table of the state table is shown in Fig. 13.28. Present State A B C D E F
Next State C 0 1 0 1 1 0
D 1 1 0 0 0 0
Output Q 0 1 0 0 1 1
Figure 13.27: Flow table of gated D flipflop
Based on the primitive flow table of the gated D flipflop is shown in Fig. 13.28. The entry with “” denotes that it is the “Don’t care” state.
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A B C D E F
00 C, 0 , C, F, 
CD 01 A, A, , , A, 
11 B, , B, B, , 
10 , E, D, 
E, 
Figure 13.28: The primitive flow table of gated D flipflop
Based on equivalency pair criterion, two states are said to be equivalent if they have the same input and output logic states. This one can see that equivalency pairs are (A, B), (A, C), (A, D), (B, E), (B, F), (C, D), and (E, F). Once the equivalency pairs are obtained, the next step is to get the maximal equivalency state by merger diagram. The merger diagram is a graph in which each state is represented by a dot placed along the circumference of a circle. Lines are drawn between any two corresponding dots that form equivalency pair. All possible equivalency states can be obtained from the merger diagram by observing the geometrical patterns in which states are connected to each other. nstate equivalency set is represented by a nsided polygon with diagonals connected. The merger diagram of the equivalency pairs obtained from the above example is shown in Fig. 13.29.
Figure 13.29: Merger diagram of the example shown in Fig. 13.28  177 
13 Asynchronous Sequential Network
The maximal equivalency states shall be (A, B), (A, C, D), and (B, E, F). The next procedure is to check the closed covering condition of the equivalency. If the equivalency set cover all original states then the equivalencies are considered as closed. Leaving equivalency pair (A, B), (A, C, D) and (B, E, F) equivalency sets cover all states. It is consider closed covering. If there is no implied state or if the implies states are includes within the equivalency set, the equivalency set is considered as closed covering. Leaving equivalency pair (A, B) is considered closed covering since state A and B are already covered in (A, C, D) and (B, E, F) equivalency sets. Consider the merger diagram shown in Fig. 13.29 that has equivalency pair (A, B), (A, D), (B, C), (C, D), (C, E), and (D, E). Based on the result shown in Fig. 13.30, the equivalency sets are (A, B), (A, D), (B, C), and (D, E). The equivalency sets are closed. If removing (A, D) equivalency set is also closed. But this does not has closed covering because (A, D) equivalency pair is not covered by the remaining equivalency sets.
Figure 13.30: Merger diagram
13.5 State Assignment State assignment for synchronous network circuit has the objective to reduce the logic state. State assignment for asynchronous network is aimed to avoid critical race.  178 
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Race exists in asynchronous network circuit when two or more state variables change during state transition. A race is considered noncritical if the correct stable next state is eventually reached during state transition. Take for an example the partial flow table shown in Fig. 13.31 has noncritical race because the expected final state of 11 is eventually reached when CD changes from 00 to 01. Next State Present CD Value State 00 01 10 11 ymys YmYs 00 11 01 11 10 11 11 Figure 13.31: A partial flow table showing non critical race
When CD changes state from 00 to 01, the output YmYs will change from 00 to 11. However, it depends on whether Ym changes before Ys or Ym after Ys or at the same time. If Ym changes before Ys, then ymys shall be 10. This will cause YmYs to transition to 11. This in turns will cause input ymys to change to 11 and eventually stable state 11 is attained. If Ys changes before Ym, then YmYs shall be transition to 01. This causes ymys to change to 01 and in turns transit YmYs to 11. Since YmYs is equal to 11 then ymys shall be equal to 11 and eventually YmYs stays at stable state 11. One can see that the transition is non critical because the expected final stable state of 11 is eventually reached. Partial flow table shown in Fig. 13.32 has critical race because the expected final stable state of 11 may not be reached when CD changes from 00 to 01. It depends on the race condition. If Ym changes after Ys, then YmYs shall be 01 and the stable state shall eventually be 01. If Ym changes before Ys, then stable state shall be 10. If both Ym and Ys change at the same time, then the stable state shall be 11 as expected.
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Present State
00
ymys 00 01 10 11
Next State CD Value 01 10 YmYs 11
11
Figure 13.32: A partial flow table showing non critical race
Let’s consider another condition of race called cycle. A cycle occurs when an asynchronous network makes a transition through a series of unstable states in the cyclic manner. An example is the partial flow table of a network circuit shown in Fig. 13.33. At stable state 11 conditions, changing CD value from 01 to 11 would result a cycle race and the network will never attain the stable state condition. The sequence of YmYs is
Present State
00
ymys 00 01 10 11
Next State CD Value 01 10 YmYs 10 01 11 10 01 00 10
11
Figure 13.33: A partial flow table showing cycle race condition
The technique commonly used for making a critical racefree network is state assignment. State assignments are classified as follows. • Shared state assignment • Multiple row state assignment • One hot state assignment  180 
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Tutorials 13.1. Explain the difference between asynchronous and synchronous sequential circuits. 13.2. An asynchronous sequential circuit is described by the excitation and output functions Y= X1 X 2 + (X1 + X 2 )⋅ y and z = y. (i). Draw the logic diagram of the circuit. (ii). Derive the transition table and output map. (iii). Obtain a twostate flow table. (iv). Describe in words the behavior of the circuit. 13.3. From the transition table of SR flipflop, show that the circuit is unstable when all three inputs are equal to 1.
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References 1. Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with Verilog Design”, McGrawHill, 2003. 2. M. Morris Mano, “Digital Design”, Third edition, Prentice Hall, 2002. 3. Donald D. Givone, “Digital Principles and Design”, McGraw Hill 2003. 4. John M. Yarbrough, “Digital Logic Applications and Design”, PWS Publishing Co., 1997.
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