C2.3.

Write a sequence of MIPS assembly code that will detect overflow for unsigned subtraction. Hint: overflow occurs when the operation’s result falls outside the valid range. (assuming $t1-$t2) ble $t1,$t2,ovf

Bonus answer: Write a sequence of MIPS assembly code that will detect overflow for signed subtraction. Hint: overflow occurs when the operation’s result falls outside the valid range. subu $t0,$t1,$t2 xor $t3,$t1,$t2 beqz $t3,no_ovf xor $t3,$t0,$t1 beqz $t3, no_ovf ovf: (overflow code) j out no_ovf: (no overflow code) out: C2.4.

Write a MIPS assembly-language subroutine having the following requirements. The subroutine takes two arguments, in $a0 and $a1, which hold the base memory addresses of two equal-sized arrays, and a third argument in $a2 that holds the arrays’ lengths. The subroutine’s function is to copy the contents of the first array into the second array but in reverse order. This subroutine also must preserve the values of all the caller’s registers. (assuming array is of bytes) rev:

loop:

addi $sp,$sp,-16 sw $t0,0($sp) sw $t1,4($sp) sw $t2,8($sp) sw $t3,12($sp) li $t0,0 move $t1,$a2 addi $t1,$t1,-1 add $t2,$a0,$t0 lb $t3,0($t2) add $t2,$a1,$t1 sb $t3,0($t2) addi $t0,$t0,1 addi $t1,$t0,-1 bne $t0,$a2,loop lw $t0,0($sp) lw $t1,4($sp) lw $t2,8($sp) lw $t3,12($sp) addi $sp,$sp,16 jr $31

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C2.7.

Assume there is a MIPS pseudoinstruction named ADD64 rd, rs, rt that performs a 64-bit integer addition. The instruction ADD64 $2, $4, $6 combines registers $4 and $5 to form one 64-bit operand (i.e. $4 is high-order 32 bits and $5 is low-order 32 bits) and combines registers $6 and $7 as the other 64-bit operand. The result would be stored in a 64-bit register spanning register $2 and $3. Translate this pseudocode instruction. Hint: Think of how you perform binary addition on paper. addu $2,$4,$6 addu $3,$5,$7 nor $1,$5,$0 sltu $1,$t1,$7 bnez $1,carryin j out carryin:addi $2,$2,1 out:

C2.9.

Many CISC instruction set architectures, such as Intel IA-32 (x86) and IBM 360, include a set of instructions that do computation using a datatype called binary-coded decimal (BCD). BCD stores integer values by assigning binary-encoded decimal values (0-9) into 4-bit fields. Eight of these 4-bit fields can be packed into a 32-bit word, representing a value between 0 and 99,999,999. For example, the (16-bit) value 0011 1001 0001 0101 represents 3,915 (instead of 14,613 as it would as a regular base-2 integer). Assume we have a pseudoinstruction called CBCD rd, rs that converts the binary value in register rs to an 8-digit packed BCD value written to register rd. Show (for full credit) or describe (for partial credit) how CBCD $2, $3 could be translated into MIPS instructions. Hint: how would you perform this base conversion yourself? srl $2,$3,24 li $1,10 mult $2,$2,$1 sll $3,$3,8 srl $1,$3,24 add $2,$2,$1 li $1,10 mult $2,$2,$1 sll $3,$3,8 srl $1,$3,24 add $2,$2,$1 li $1,10 mult $2,$2,$1 sll $3,$3,8 srl $1,$3,24 add $2,$2,$1 li $1,10 mult $2,$2,$1

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C2.10. Write a sequence of MIPS assembly instructions that will swap the values of registers $s0 and $s1 without using any additional registers or any loads and stores. Hint: this requires that you use the XOR instruction. xor $s0,$s0,$s1 xor $s1,$s0,$s1 xor $s0,$s0,$s1 C2.14. Convert the following assembly-language instruction to machine instruction(s) represented in hexadecimal. Assume the data segment of the program starts at 1010 010016 and that INPUT is offset from the beginning of the data segment by 24 bytes. Also assume that register $1 is the only register you may use for resolving pseudoinstructions. lb $2,INPUT+2($3) Note: the opcode for lb is 2016. First, we need to convert this statement to assembly language... lui $1,0x1010 ori $1,$1,0x0100 add $1,$1,$3 addi $1,$1,2 lb $2,24($1) Next, we need to encode the instructions... 0x3c011010 0x34210100 0x00230820 0x20210002 0x80220018 Because I only provided the opcode for lb, you will receive full credit for this question if you encoded the lb (regardless of the registers used in the instruction). C2.15. MIPS has the following pseudoinstruction defined, as part of its interface spec: ror rdest, rsrc1, rsrc2 This instruction performs a rotate. That is, it is a right shift but the bits that are shifted in from the left are the same bits that are shifted out from the right. The source register is defined by rsrc1 and the rotate distance is defined in rsrc2. How would the following instruction be translated into nonpseudo-MIPS assembly language? Remember, pseudoinstruction translation uses register 1 as a temporary register. ror $2, $3, $4 sub $1,$0,$4 sllv $1,$3,$1 srlv $2,$3,$4 or $2,$2,$1 C2.18. Write a recursive assembly language routine called printover that takes the address of a 50-element halfword array and an integer as arguments. The routine iterates through the array, calling another routine called over for every element that is greater than the integer sent in as printover’s second argument. over’s arguments are the index of an element

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and its value. over has no return value, but printover returns the number of elements found. You only have to write printover. You may assume that over will not destroy any $a or $s registers. printover must save any registers that it destroys on the MIPS stack before doing anything else. Provide reasonable commentting for your code. printover:

loop:

skip:

addi $sp,$sp,-32 sw $ra,0($sp) sw $s0,4($sp) sw $s1,8($sp) sw $s2,12($sp) sw $s3,16($sp) sw $s4,20($sp) sw $s5,24($sp) sw $s6,28($sp) li $s0,0 li $s1,100 li $s4,0 move $s5,$a0 move $s6,$a1 add $s2,$s5,$s0 lh $s3,0($s2) ble $s3,$s6,skip addi $s4,$s4,1 move $a0,$s0 move $a1,$s3 jal over addi $s0,$s0,2 blt $s0,$s1,loop move $v0,$s4 lw $ra,0($sp) lw $s0,4($sp) lw $s1,8($sp) lw $s2,12($sp) lw $s3,16($sp) lw $s4,20($sp) lw $s5,24($sp) lw $s6,28($sp) addi $sp,$sp,32 jr $ra

# index # loop bound # no. times over called # array base # num. to compare # compute eff. address in $s2 # load into $s3 # skip if $s3