Application Note
TD-SCDMA Test MG3700A
Vector Signal Generator
Application Note - TD-SCDMA Test Anritsu
March 2007 (2.00)
MG3700A-E-F-10
Slide 1
Contents
• • • •
Physical Channel Basics BS Test UE Test Additional Information
MG3700A-E-F-10
3 25 51 74
Slide 2
1
What is TD-SCDMA? • • •
TD-SCDMA (Time Division Synchronous Code Division Multiple Access) is one of the five IMT-2000 standards accepted by the ITU. The radio access interface of the UMTS (UTRA) comprises two standards for operation in the FDD and TDD modes. 3GPP standardizes three systems: » W-CDMA » TD-CDMA •
UTRA FDD UTRA TDD-HCR (High Chip Rate / Higher Chip Rate)
3.84 Mcps, 5 MHz bandwidth / 7.68 Mcps, 10 MHz bandwidth
» TD-SCDMA •
UTRA TDD-LCR (Low Chip Rate)
1.28 Mcps, 1.6 MHz bandwidth
FDD TDD
Slide 3
MG3700A-E-F-10
UTRA/TDD Frequency Bands Operating Band
Bandwidth [MHz]
Uplink/Downlink [MHz]
a
20 + 15
1900 – 1920 2010 – 2025
b
60 + 60
1850 – 1910 1930 – 1990
c
20
1910 – 1930
d
50
2570 – 2620
MG3700A-E-F-10
2
Slide 4
China
HSPA Standardization in 3GPP • HSDPA (High-speed Downlink Packet Access) was standardized in 3GPP Release 5. » The downlink peak data rate will increase to 2.8 Mbps. » HS-DSCH – – – –
HARQ for downlink Fast BTS downlink scheduling Shorter downlink TTI Higher order and adaptive modulation
Slide 5
MG3700A-E-F-10
HSDPA UE Capabilities (Categories) •
3GPP TS 25.306 specifies UE capabilities for HS-DSCH categories.
MG3700A-E-F-10
Category
Maximum Number of HSPDSCH Codes per Timeslot
Maximum Number of HSPDSCH Timeslots per TTI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
12 12 12 16 16 16 12 12 12 16 16 16 16 16 16
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
Maximum Number of Transport Channel Bits per HS-DSCH TTI 7008 7008 7008 7008 7008 7008 10204 10204 10204 10204 10204 10204 14034 14034 14034
Achievable Maximum Data Rate [Mbps]
1.4 1.4 1.4 1.4 1.4 1.4 2 2 2 2 2 2 2.8 2.8 2.8
Slide 6
3
Mapping of Transport Channels onto Physical Channels Transport Channels – DCH – BCH – PCH – FACH – RACH – USCH – DSCH
HSDPA
– HS-DSCH
MG3700A-E-F-10
Physical Channels – DPCH Dedicated Physical Channel – P-CCPCH Primary Common Control Physical Channel – S-CCPCH Secondary Common Control Physical Channel – PICH Paging Indicator Channel – MICH MBMS Indication Channel – PLCCH Physical Layer Common Control Channel – PRACH Physical Random Access Channel – PUSCH Physical Uplink Shared Channel – PDSCH Physical Downlink Shared Channel – DwPCH Downlink Pilot Channel – UpPCH Uplink Pilot Channel – FPACH Fast Physical Access Channel – HS-PDSCH High Speed Physical Downlink Shared Channel – HS-SCCH Shared Control Channel for HS-DSCH – HS-SICH Shared Information Control for HS-DSCH
Slide 7
Basic Physical Channels DwPCH P-CCPCH S-CCPCH PICH DPCH PRACH UpPCH DPCH
MG3700A-E-F-10
4
Slide 8
HSDPA Physical Channels HS-SCCH HS-PDSCH HS-SICH (DPCH)
Slide 9
MG3700A-E-F-10
Frame, Burst 10 ms Frame #i
Frame #i+1
6,400 chips 5 ms Subframe #1
Subframe #2
864 chips 675 us Timeslot #0
Timeslot #1
Timeslot #2
Timeslot #3
Data symbols 352 chips
GP 32
SYNC-DL 64 chips
DwPTS 96 chips 75 us
GP 96 chips
SYNC-UL 128 chips
Timeslot #4
Midamble 144 chips Spreading factor (Q) 1 2 4 8 16
GP 32
UpPTS 160 chips 125 us
• Example
Timeslot #5
Timeslot #6
Data symbols 352 chips
GP 16
Number of symbols (N) per data field in Burst 352 176 88 44 22 5 ms
symmetric DL/UL allocation
– DwPTS:Downlink Pilot Time Slot – UpPTS: Uplink Pilot Time Slot – GP: Guard Period
5 ms
asymmetric DL/UL allocation
MG3700A-E-F-10
Slide 10
5
Mapping of Transport Blocks onto Physical Bearer DTCH (TTI 20 ms)
DCCH (TTI 40 ms)
Transport Block(s)
Transport Block(s)
Transport Block(s)
Coded Bits
Coded Bits
Coded Bits
Code 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 1 2 3 4 5 6 0 1 2 3 4 5 6 TS# Subframe Subframe #2n #2n+1 Frame #n
0 1 2 3 4 5 6 0 1 2 3 4 5 6 Subframe Subframe #2(n+1) #2(n+1)+1 Frame #n+1
0 1 2 3 4 5 6 0 1 2 3 4 5 6 Subframe #2(n+2)
Subframe #2(n+2)+1 Frame #n+2
0 1 2 3 4 5 6 0 1 2 3 4 5 6 Subframe Subframe #2(n+3) #2(n+3)+1 Frame #n+3
Slide 11
MG3700A-E-F-10
Downlink Physical Channels • Common Channels » DwPCH is a synchronization channel that is equal to the DwPTS. It is transmitted at each subframe with an antenna pattern configuration which provides whole cell coverage. Furthermore it is transmitted with a constant power level that is signalled by higher layers. The SYNC_DL code is not scrambled. » P-CCPCH and S-CCPCH are common physical channels intended for carrying system and cell information and messages for UEs when a dedicated channel is not in place for communication. » PICH is a channel that exists only at the physical layer. It is used to notify UEs of the outstanding paging messages on the Paging Channel (PCH).
MG3700A-E-F-10
6
Slide 12
Downlink Physical Channels • Common Channels » FPACH is used by BS to carry (in one burst) the acknowledgement of a detected signature with timing and power level adjustment indication to a UE. It uses of one code with SF 16, so its burst is composed of 44 symbols. The spreading code, training sequence, and timeslot position are configured by the network and signalled on the BCH. » PDSCH is a shared channel across all users requesting packet data services. Each cell may support one or more PDSCHs. The theoretical peak data rate is about 2 Mbps. » MICH is a physical channel used to carry the MBMS notification indicators. The UE may use multiple MICH within the MBMS modification period to make decisions about individual MBMS notification indicators. – MBMS: Multimedia Broadcast and Multicast Service
Slide 13
MG3700A-E-F-10
Downlink Physical Channels • Common Channels » HS-PDSCH is a shared channel across all users requesting HSDPA specific high-speed packet data services. Each cell may support one or more HS-PDSCHs. Sharing of the HS-PDSCH is based on Time Division Multiplexing (TDM) across multiple users. It uses 16QAM modulation. » HS-SCCH is a control channel associated with HS-PDSCH. It conveys the HS-PDSCH allocation information, including the user identity, SF, and modulation scheme.
• Dedicated Channels » DPCH is the dedicated physical channel for transport of information between the network and UE using a dedicated link on the physical channel.
MG3700A-E-F-10
Slide 14
7
Uplink Physical Channels • Common Channels » UpPCH is a synchronization channel that is equal to the UpPTS. It is sent by the UE. It is used for BS to determine the received power level and timing. The SYNC_UL code is not scrambled. » PRACH is shared by UEs. It is used for initial access of the system. » PUSCH is used to carry bursty traffic for packet transmission. » HS-SICH carries the feedback signalling related to downlink HSDSCH (incoming packets). The HS-DSCH-related feedback signalling consists of Hybrid-ARQ Acknowledgement (HARQACK) and Channel-Quality Indication (CQI).
Slide 15
MG3700A-E-F-10
Uplink Physical Channels • Dedicated Channels » DPCH is the dedicated physical channel for transport of information between the network and UE using a dedicated link on the physical channel.
MG3700A-E-F-10
8
Slide 16
Timeslot Formats for Downlink QPSK Slot Format #
Spreading Factor
Midamble length (chips)
code word
0 1 2 3 4 5
16 16 16 16 16 16
144 144 144 144 144 144
0 4 8 16 32 0
0&0 0&0 0&0 0&0 0&0 2&2
88 88 88 88 88 88
6 7 8 9
16 16 16 16
144 144 144 144
4 8 16 32
2&2 2&2 2&2 2&2
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
144 144 144 144 144 144 144 144 144 144 144 144 144 144 144
0 4 8 16 32 0 4 8 16 32 0 4 8 16 32
0&0 0&0 0&0 0&0 0&0 2&2 2&2 2&2 2&2 2&2 32 & 32 32 & 32 32 & 32 32 & 32 32 & 32
NTFCI
NSS & NTPC (bits)
Bits/slot
NData/Slot (bits)
Ndata/data
Ndata/data
field(1)
field(2)
(bits)
(bits)
88 86 84 80 72 84
44 42 42 40 36 44
44 44 42 40 36 40
88 88 88 88
82 80 76 68
42 42 40 36
40 38 36 32
1408 1408 1408 1408 1408 1408 1408 1408 1408 1408 1408 1408 1408 1408 1408
1408 1406 1404 1400 1392 1404 1402 1400 1396 1388 1344 1342 1340 1336 1328
704 702 702 700 696 704 702 702 700 696 704 702 702 700 696
704 704 702 700 696 700 700 698 696 692 640 640 638 636 632
(bits)
Slide 17
MG3700A-E-F-10
Timeslot Formats for Uplink QPSK Slot Format #
Spreading Factor
Midamble length (chips)
code word
0 1 2 3 4 5 6 7 8 9
16 16 16 16 16 16 16 16 16 16
144 144 144 144 144 144 144 144 144 144
0 4 8 16 32 0 4 8 16 32
0&0 0&0 0&0 0&0 0&0 2&2 2&2 2&2 2&2 2&2
88 88 88 88 88 88 88 88 88 88
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
144 144 144 144 144 144 144 144 144 144 144 144 144 144 144
0 4 8 16 32 0 4 8 16 32 0 4 8 16 32
0&0 0&0 0&0 0&0 0&0 2&2 2&2 2&2 2&2 2&2 4&4 4&4 4&4 4&4 4&4
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
144 144 144 144 144 144 144 144 144 144 144 144 144 144 144
0 4 8 16 32 0 4 8 16 32 0 4 8 16 32
0&0 0&0 0&0 0&0 0&0 2&2 2&2 2&2 2&2 2&2 8&8 8&8 8&8 8&8 8&8
MG3700A-E-F-10
NTFCI
NSS & NTPC (bits)
Bits/slot
NData/Slot (bits)
Ndata/data
Ndata/data
field(1)
field(2)
(bits)
(bits)
88 86 84 80 72 84 82 80 76 68
44 42 42 40 36 44 42 42 40 36
44 44 42 40 36 40 40 38 36 32
176 176 176 176 176 176 176 176 176 176 176 176 176 176 176
176 174 172 168 160 172 170 168 164 156 168 166 164 160 152
88 86 86 84 80 88 86 86 84 80 88 86 86 84 80
88 88 86 84 80 84 84 82 80 76 80 80 78 76 72
352 352 352 352 352 352 352 352 352 352 352 352 352 352 352
352 350 348 344 336 348 346 344 340 332 336 334 332 328 320
176 174 174 172 168 176 174 174 172 168 176 174 174 172 168
176 176 174 172 168 172 172 170 168 164 160 160 158 156 152
(bits)
Slot Format #
Spreading Factor
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
NTFCI
NSS & NTPC (bits)
Bits/slot
Midamble length (chips)
code word
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
144 144 144 144 144 144 144 144 144 144 144 144 144 144 144
0 4 8 16 32 0 4 8 16 32 0 4 8 16 32
0&0 0&0 0&0 0&0 0&0 2&2 2&2 2&2 2&2 2&2 16 & 16 16 & 16 16 & 16 16 & 16 16 & 16
704 704 704 704 704 704 704 704 704 704 704 704 704 704 704
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
144 144 144 144 144 144 144 144 144 144 144 144 144 144 144
0 4 8 16 32 0 4 8 16 32 0 4 8 16 32
0&0 0&0 0&0 0&0 0&0 2&2 2&2 2&2 2&2 2&2 32 & 32 32 & 32 32 & 32 32 & 32 32 & 32
1408 1408 1408 1408 1408 1408 1408 1408 1408 1408 1408 1408 1408 1408 1408
NData/Slot (bits)
Ndata/data
Ndata/data
field(1)
field(2)
(bits)
(bits)
704 702 700 696 688 700 698 696 692 684 672 670 668 664 656
352 350 350 348 344 352 350 350 348 344 352 350 350 348 344
352 352 350 348 344 348 348 346 344 340 320 320 318 316 312
1408 1406 1404 1400 1392 1404 1402 1400 1396 1388 1344 1342 1340 1336 1328
704 702 702 700 696 704 702 702 700 696 704 702 702 700 696
704 704 702 700 696 700 700 698 696 692 640 640 638 636 632
(bits)
Slide 18
9
Timeslot Formats for Downlink and Uplink 8PSK Midamble length (chips)
NTFCI
NSS & NTPC (bits)
Bits/slot
NData/Slot (bits)
Ndata/data
Ndata/data
Slot Format #
Spreading Factor
0 1
1 1
144 144
0 6
0&0 0&0
2112 2112
2112 2109
1056 1053
1056 1056
2 3 4 5 6 7 8 9 10 11 12 13
1 1 1 1 1 1 1 1 1 1 1 1
144 144 144 144 144 144 144 144 144 144 144 144
12 24 48 0 6 12 24 48 0 6 12 24
0&0 0&0 0&0 3&3 3&3 3&3 3&3 3&3 48 & 48 48 & 48 48 & 48 48 & 48
2112 2112 2112 2112 2112 2112 2112 2112 2112 2112 2112 2112
2106 2100 2088 2106 2103 2100 2094 2082 2016 2013 2010 2004
1053 1050 1044 1056 1053 1053 1050 1044 1056 1053 1053 1050
1053 1050 1044 1050 1050 1047 1044 1038 960 960 957 954
14
1
144
48
48 & 48
2112
1992
1044
948
15 16 17 18 19 20 21 22 23 24
16 16 16 16 16 16 16 16 16 16
144 144 144 144 144 144 144 144 144 144
0 6 12 24 48 0 6 12 24 48
0&0 0&0 0&0 0&0 0&0 3&3 3&3 3&3 3&3 3&3
132 132 132 132 132 132 132 132 132 132
132 129 126 120 108 126 123 120 114 102
66 63 63 60 54 66 63 63 60 54
66 66 63 60 54 60 60 57 54 48
code word
(bits)
field(1)
field(2)
(bits)
(bits)
Slide 19
MG3700A-E-F-10
Midamble •
The data fields are separated by a midamble that is used for channel estimation. » The midamble is used for both channel equalisation and coherent detection at the receiver. It reduces the user data payload.
•
The scrambling code and basic midamble code are broadcast and may be constant within a cell.
•
The midambles, i.e. the training sequences of different users, are time-shifted versions of one periodic basic code. Different cells use different periodic basic codes, i.e. different midamble sets.
» The same basic midamble code is used throughout the frame.
Code c(N) Code c(2) Code c(1)
Timeslot
MG3700A-E-F-10
10
Data symbols 352 chips
Code c(N) Midamble m(1)
Midamble 144 chips
Slide 20
Code c(2) Code 1
Data symbols 352 chips
GP 16
Midamble •
Association between Midambles and Channelisation Codes for K=8 m(1) - c16 (1)
m(1) - c8 (1)
m(2) - c8 (2)
- c8
m(2) - c16 (4)*
(3)
- c1
Group 1
SYNC-UL ID 0...7
Group 2
1
8...15
Group 32
31
248...255
m(3) - c16 (6)* m(4) - c16 (7)
m(4) - c8 (4) m
Associated Codes SYNC-DL ID 0
m(3) - c16 (5)
m(3) - c4 (2)
(1)
Code Group
m(2) - c16 (3)
m(1) - c2 (1) m
Code Allocation
m(1) - c16 (2)*
m(1) - c4 (1)
(3)
•
Scrambling Code ID 0 1 2 3 4 5 6 7 . . .
Basic Midamble Code ID 0 1 2 3 4 5 6 7
124 125 126 127
124 125 126 127
m(4) - c16 (8)*
(1)
m(5) - c16 (9)
m(5) - c8 (5)
m(5) - c16 (10)*
m(5) - c4 (3)
m(6) - c16 (11)
m(6) - c8 (6)
m(6) - c16 (12)*
m(5) - c2 (2)
m(7) - c16 (13)
m(7) - c8 (7)
m(7) - c16 (14)*
m(7) - c4 (4)
k: User number 1 to K K: Maximum users 2, 4, 6, 8, 10, 12, 14, 16
m(k)
m(8) - c16 (15)
m(8) - c8 (8)
m(8) - c16 (16)*
Secondary channelisation codes are marked with *. In timeslot 0 the number of midambles K=8. In all of the other timeslot, K is individually configured from higher layers.
k: Channelisation Code number 1 to Q Q: SF 1, 2, 4, 8, 16
cQ(k)
Slide 21
MG3700A-E-F-10
TFCI •
TFCI (Transmission Format Combination Indicator) is used to indicate the combination of used transport channels in DPCH and is sent only once per frame. TFCI uses in-band signalling and has its own coding. The number of TFCI bits is variable and is set at the beginning of the call. TFCI is always present in the first timeslot in a radio frame for each CCTrCH (Coded Composite Transport Channel).
•
» TFCI is transmitted in the data parts of the respective physical channel, meaning that TFCI code word bits and data bits are subject to the same spreading procedure. » TFCI code word bits are equally distributed between the two subframes and respective data fields. 1
st
part of TFCI code word
Data symbols
2
nd
part of TFCI code word G
Midamble
Data symbols
P
3
rd
part of TFCI code word
TFCI code word G
Data symbols
Time slot x (864 Chips)
4 th part of
Midamble
Data symbols
P
1 st part of TFCI code word
Data symbols
Time slot x (864 Chips)
Sub-frame 5ms
TPC symbols
symbols 3 2 nd part of TFCI code word
Midamble
Data symbols
G P
Sub-frame 5ms
rd
TPC part of TFCI code word SS symbols
Data symbols
Time slot x (864 Chips)
symbols 4 th part of TFCI code word
Midamble
Data symbols
G P
Time slot x (864 Chips)
Sub-frame 5ms
Sub-frame 5ms Radio Frame 10ms
Radio Frame 10ms
in case of no TPC and SS
MG3700A-E-F-10
SS
in case of TPC and SS
Slide 22
11
TPC • •
TPC (Transmitter Power Control) is transmitted in the data parts of the traffic burst in uplink and downlink. For every user, the TPC information is transmitted at least once per subframe. SS symbol(s) Data symbols
TPC symbol(s)
Midamble
Data symbols
GP
144 chips 864 Chips
•
The length of the TPC command is one symbol. • TPC bit for QPSK bTPC 0 1
TPC command 'Down' 'Up'
Meaning Decrease Tx Power Increase Tx Power
• TPC bit for 8PSK TPC Bits 000 110
TPC command 'Down' 'Up'
Meaning Decrease Tx Power Increase Tx Power
Slide 23
MG3700A-E-F-10
SS • • •
SS (Synchronisation Shift) is transmitted in the data parts of the traffic burst in downlink and uplink. For every user, the SS information is transmitted at least once per transmitted subframe. SS is utilized to command a timing adjustment by k/8 × Tc. – Tc: 1.28 Mcps -1 = 781.25 ns SS symbol(s) Data symbols
Midamble
Data symbols
144 chips 864 Chips
•
The length of the SS command is one symbol. • SS bit for QPSK SS Bits 00 11 01
SS command 'Down' 'Up' ‘Do nothing’
Meaning Decrease synchronisation shift by k/8 Tc Increase synchronisation shift by k/8 Tc No change
• SS bit for 8PSK SS Bits 000 110 011
MG3700A-E-F-10
12
SS command 'Down' 'Up' ‘Do nothing’
Meaning Decrease synchronisation shift by k/8 Tc Increase synchronisation shift by k/8 Tc No change
Slide 24
GP
BS Test 3GPP 6 7 8
TS 25.142 (Release 7) Transmitter Receiver Performance requirements Wanted Signal Generator with BERT
Test
Interference Signal Generator
CW AWGN Others Generator Generator Spectrum Analyzer Circulator
6.7
Transmit intermodulation
MG3700A
7.2 7.3 7.4 7.5
Reference sensitivity level Dynamic range Adjacent Channel Selectivity (ACS) Blocking characteristics
* *
7.6
Intermodulation characteristics
*
8.2
Demodulation in static propagation conditions
*
8.3
Demodulation of DCH in multipath fading conditions
MG3700A
*
MG3700A
MG3692B 20 GHz
MA1612A
or MG3642A
3 GHz Combiner
2.08 GHz
MA1612A 3 GHz Combiner
Fading Simulator
*: MG3700A for the wanted signal generator generates two signals with interference signal, CW or AWGN.
Unsupported interference signal pattern Unsupported HSPA
Slide 25
MG3700A-E-F-10
Receiver Test Setup Example Reference clock Wanted Signal Generator (+ Interference Signal Generator) (+ CW Generator) (+ AWGN Generator) BER Tester MG3700A
Start trigger Received DTCH data Clock Controller Terminator (MP752A)
CW Generator (MG3692B)
Combiner (MA1612A)
– Start trigger • Front panel [Start/Frame Trigger] Input – 40 ms × n clock
– Reference clock Use only one. • Rear panel [Baseband Ref Clock] Input – 1.28 MHz, 2 × 1.28 MHz (2.56 MHz), 4 × 1.28 MHz (5.12 MHz)
• Rear panel [10MHz/5MHz Ref] Input
– Controller • Makes receivable state for UL RMC by FTM (Factory Test Mode) control • Reports internal BLER calculation for received DTCH
MG3700A-E-F-10
Slide 26
13
Timing Synchronization Setup Example •
Start trigger delay » Set the timing at which the BS can receive UL RMC. DCCH
DL DCH
DCCH
DTCH
DPCH
DTCH
DTCH
DTCH
Frame
Frame
Frame
Frame
Frame
Frame
Frame
Frame
Subframe
Subframe
Subframe
Subframe
Subframe
Subframe
Subframe
Subframe
Trigger DCCH
UL DCH
DTCH 1 frame Trigger
DTCH
3 frames
Delay: 0 chip
Delay: 19,200 chips
Slide 27
MG3700A-E-F-10
Timing Synchronization Setup Example •
Setting External Start trigger » Captures/ Synchronizes trigger once only
•
Reference clock »
[Baseband Ref Clock] Input usage case – Source : [External] – Baseband Reference Clock: • [1],[1/2],[1/4],[1/8],[1/16] ×
»
[10MHz/5MHz Ref] Input usage case – Source : [Internal]
•
Trigger recapture/ synchronization
MG3700A-E-F-10
14
Slide 28
Scrambling Code Synchronization Setup Example •
Scrambling code » Each basic midamble code is associated with a cell-specific complex scrambling code. – Created from 16-bit long complex scrambling sequences
» Applies to scrambling (spreading)
•
Set the scrambling code and basic midamble code to BS. – 0 Code Group
Associated Codes
Group 1
SYNC-DL ID 0
SYNC-UL ID 0...7
Group 2
1
8...15
Group 32
31
248...255
Scrambling Code ID 0 1 2 3 4 5 6 7 . . .
Basic Midamble Code ID 0 1 2 3 4 5 6 7
124 125 126 127
124 125 126 127
Slide 29
MG3700A-E-F-10
Wanted Signal Setup Example Test – Receiver excluding Dynamic range
•
UL RMC 12.2 kbps
Setting power level is the Mean power.
Mean power is the power in a bandwidth of at least (1+α) times 1.28 MHz chip rate. The measurement period is a transmit timeslot excluding the guard period. RRC filtered mean power is the power measured through a root raised cosine filter with roll-off α=0.22 and 1.28 MHz chip rate bandwidth. For a perfectly modulated signal, RRC filtered mean power = Mean power - 0.246 dB
MG3700A-E-F-10
Slide 30
15
Wanted Signal + Interference Signal Setup Example Test – ACS – Blocking characteristics – Intermodulation characteristics
•
UL RMC 12.2 kbps +
•
Interferer
ACS: 1.6 MHz offset Blocking: ≥ 3.2 MHz offset Intermodulation:6.4 MHz offset
» Set Frequency offset.
Unsupported interference signal pattern
– -31.9872 ∼ +31.9872 MHz
MG3700A-E-F-10
Slide 31
Interference Signal The interference signal is equivalent to a continuous wideband CDMA signal with one code of chip frequency 1.28 Mcps, filtered by an RRC transmit pulse-shaping filter with roll-off α = 0.22.
MG3700A-E-F-10
16
Slide 32
Wanted Signal + AWGN Setup Example Test – Dynamic range
•
UL RMC 12.2 kbps
•
AWGN
+
Test – Performance requirements
•
UL RMC 12.2 kbps – DPCHo multiplexing
•
UL RMC 64 kbps
•
UL RMC 144 kbps
•
UL RMC 384 kbps
– DPCHo multiplexing – DPCHo multiplexing
+
•
Test Number
AWGN
Iˆor [dB] I oc
BLER
0.6 -0.9 -0.4 -0.3 -0.1 0.5 0.6
10 -1 10 -2 10 -1 10 -2 10 -1 10 -2 10
1
» Ioc [dBm/1.28MHz]
2 3 4
A/B Set
A level
B level
RF level
A
Variable
Static
Coupled
B
Static
Variable
Coupled
Constant
Variable
Variable
Static
-2
Slide 33
MG3700A-E-F-10
DPCHo DPCHo simulates an individual intra-cell interferer that is equivalent to a valid UTRA TDD signal with SF 8, using the same time slot(s) as the wanted signal and applying the same cell-specific scrambling code. Parameters Number of DPCHo Spread factor of DPCHo
Unit
DPCH o _ E c I or Wide Area BS Local Area BS Information Data Rate
Ioc
Test Number
1 2 3 4
Test 2 1 8 -7
dBm/1,28 MHz dBm/1,28 MHz kbps
12,2
64
BLER objective
Number of DPCH0
10 -1 10 -2 10 -1 10 -2 10 -1 10
-2
4 1 1 1 1 0
-2
0
10
MG3700A-E-F-10
dB
Test 1 4 8 -7
Test 3 1 8 -7
Test 4 0
144
384
–
-91 -77
Power of each DPCH0 measured at the BS antenna connector [dBm] Wide Local Area BS Area BS -97.4 -83,4 -98.9 -84,9 -98.4 -84,4 -98.3 -84,3 -98.1 -84,1 – – –
–
Parameters of the wanted signal DPCH
SF
DPCH1 DPCH1 DPCH1 DPCH1 DPCH1 DPCH1 DPCH2 DPCH1 DPCH2
8 2 2 2 2 8 2 8 2
Power measured at the BS antenna connector [dBm] Wide Local Area BS Area BS -97.4 -83,4 -92.9 -78,9 -92.5 -78,5 -92.3 -78,3 -92.1 -78,1 -97.5 -83,5 -91.5 -77,5 -97.4 -83,4 -91.4 -77,4
Slide 34
17
UL RMC 12.2 kbps
DPCH
Parameter Information data rate RU´s allocated Midamble Interleaving Power control TFCI Synchronisation Shift (SS) Inband signalling DCCH Puncturing level at Code rate 1/3 : DCH of the DTCH/ DCH of the DCCH
Value 12.2 kbps 1TS (1*SF8) = 2RU/5ms 144 20 ms 4 Bit/user/10ms 16 Bit/user/10ms 4 Bit/user/10ms 2.4 kbps 33% / 33%
DPCH1 DPCHo
Slide 35
MG3700A-E-F-10
UL RMC 12.2 kbps MAC-Header
DTCH
244
Information
244
CRC
16
8
1st
804bit/20m
Rate
352 bit
gross
352 bit
- TFCI - TPC - SS
- 16 bit - 4 bit - 4 bit
- TFCI - TPC - SS
- 16 bit - 4 bit - 4 bit
-
- 60 bit
-
- 60 bit
puncturing
268 bit
puncturing
268 bit
328
TFCI, TPC and
176
Physical Channel
SF=8
84 4
144 4 4 80 chip
TFCI
268
268
60
16
8
176
84 4
144 4 4 80 chip
328
176
84 4
144 4 4 80 chip
268
268
328
60
268
328
16
8
176
84 4
328
84 4
144 4 4 80 chip
60
60
328
16
176
144 4 4 80 chip
Puncturing Level: Rate Matching
8
176
84 4
144 4 4 80 chip
328
176
84 4
144 4 4 80 chip
16
8
176
84 4
144 4 4 80 chip
TFCI TPC & SS
Sub Frame #1
18
60
328
2st
360bit
402 bit puncturing to 268 Puncturing Level: 4 RU = 88 * 4 = 352 Bits
268
Sub Frame #2
Sub Frame #3
Sub Frame #4
Sub Frame #5
Slide 36
8
402
gross
268
Service
12
(112+8)*3=36
402
402 bit puncturing to 268 Puncturing Level: 4 RU = 88 * 4 = 352 Bits
DCCH
112
804bit/20m
402
268
96
100
8
(260+8)*3=80
402
RF-
MG3700A-E-F-10
16
260bit/20m
(260+8)*3=80
Conv. Coding
Slot
4
244
260bit/20m
Tail bit h
244
Sub Frame #6
Sub Frame #7
Sub Frame #8
60
60
60
UL RMC 64 kbps
DPCH1
Parameter Information data rate RU's allocated Midamble Interleaving Power control (TPC) TFCI Synchronisation Shift (SS) Inband signalling DCCH Puncturing level at Code rate: 1/3 DCH of the DTCH / ½ DCH of the DCCH
Value 64 kbps 1TS (1*SF2) = 8RU/5ms 144 20 ms 4 Bit/user/10ms 16 Bit/user/10ms 4 Bit/user/10ms 2.4 kbps 32% / 0
DPCHo
Slide 37
MG3700A-E-F-10
UL RMC 64 kbps MAC-Header
Information Data
1280
CRC attachement
1280
DTCH
1280
4
1280
16
Turbo Coding 1/3
[(640*2)+16]*3=3888
Trellis Termination
3888bit / 20ms
16
240bit
1950
1950
8
(112+8)*2=240 Convolutional Coding 1/2
12
3900bit / 20ms
1950
RF-Segmentation
12
112
3888bit / 20ms
3900bit / 20ms
1 st Interleaving
DCCH
100
[(640*2)+16]*3=3888
12
96
1950
Rate Matching 1950 bit punctured to 1324 bit Puncturing Level: 32% 16 RU = 88 * 16 = 1408 Bits available 1408 bit
gross
1408 bit
- TFCI - TPC - SS
- 16 bit - 4 bit - 4 bit
- TFCI - TPC - SS
- 16 bit - 4 bit - 4 bit
- Signalling
- 60 bit
- Signalling
- 60 bit
puncturing to
1324 bit
puncturing to
1324 bit
1324
1324
Service Multiplexing
1384
TFCI, TPC and SS
704
Physical Channel Mapping
Slot segmentation
SF=2
60
1324
1324
60
16
8
704
1384
704
16
8
1384
704
704
Puncturing Level: 0%
1324
60
1324
1384
1384
348 4 144 4 4 344 348 4 144 4 4 344 348 4 144 4 4 344 348 4 144 4 4 344 chips chips chips chips TFCI
60
60
60
60
60
1384
16
8
704
1384
704
16
8
704
348 4 144 4 4 344 348 4 144 4 4 344 348 4 144 4 4 344 348 4 144 4 4 344 chips chips chips chips
TFCI TPC & SS
Sub Frame #1
MG3700A-E-F-10
1324
1324
1384
2 st Interleaving
1950 bit punctured to 1324 bit Puncturing Level: 32% 16 RU = 88 * 16 = 1408 Bits available
gross
Sub Frame #2
Sub Frame #3
Sub Frame #4
Sub Frame #5
Sub Frame #6
Sub Frame #7
Sub Frame #8
Slide 38
19
UL RMC 144 kbps
DPCH1
Parameter Information data rate RU´s allocated Midamble Interleaving Power control TFCI Synchronisation Shift (SS) Inband signalling DCCH Puncturing level at Code rate 1/3 : DCH of the DTCH/ DCH of the DCCH
Value 12.2 kbps 1TS (1*SF8) = 2RU/5ms 144 20 ms 4 Bit/user/10ms 16 Bit/user/10ms 4 Bit/user/10ms 2.4 kbps 33% / 33%
DPCHo
Slide 39
MG3700A-E-F-10
UL RMC 144 kbps MAC-Header
Information Data
2880
CRC attachement
2880
DTCH
2880
16
4
2880
Turbo Coding 1/3
[(1440*2)+16]*3=8688
Trellis Termination
8688bit / 20ms
16
4350
8
(112+8)*2=240 Convolutional Coding 1/2
12
8700bit / 20ms
4350
RF-Segmentation
12
112
8688bit / 20ms
8700bit / 20ms
1 st Interleaving
DCCH
100
[(1440*2)+16]*3=8688
12
96
240bit
4350
4350
Rate Matching 4350 bit punctured to 2712 bit Puncturing Level: 38% 32 RU = 88 * 32 = 2816 Bits available 2816 bit
gross
2816 bit
- TFCI - TPC - SS
- 32 bit - 8 bit - 8 bit
- TFCI - TPC - SS
- 32 bit - 8 bit - 8 bit
- Signalling
- 56 bit
- Signalling
- 56 bit
puncturing to
2712 bit
puncturing to
2712 bit
2712
2712
Service Multiplexing
2 st Interleaving
2768
1408
Physical Channel Mapping
Slot segmentation
SF=2 2 Timeslots
2712
56
2712
2768
32
16
1408
2768
1408
2712
56
2712
2768
32
16
1408
2768
1408
Puncturing Level: 7% Rate Matching (224)
56
56
2768
32
16
1408
2768
1408
32
16
1408
144 144 144 144 344 172 4 144 4 4 344 172 4 144 172 4 chips 4 4 344 172 4 144 4 4 344 144 44 44344 348 4 chips4 4 344 348 4 chips4 4 344 348 4 chips4 4 344 348 4 chips chips chips chips
TFCI TPC & SS
Sub Frame #1
20
56
2712
144 4 4 344 172 4 144 4 4 344 172 4 144 4 4 344 172 4 144 4 4 344 172 4 144 144 144 144 chips chips 348 4 chips4 4 344 348 4 chips 4 4 344 348 4 chips4 4 344 348 4 chips 4 4 344 chips chips TFCI
MG3700A-E-F-10
2712
2768
TFCI, TPC and SS
4350 bit punctured to 2712 bit Puncturing Level: 38% 32 RU = 88 * 32 = 2816 Bits available
gross
Sub Frame #2
Sub Frame #3
Sub Frame #4
Sub Frame #5
Slide 40
Sub Frame #6
Sub Frame #7
Sub Frame #8
56
56
56
UL RMC 384 kbps
DPCH2
Parameter Information data rate RU's allocated
Value 384 kbps 4TS (1*SF2 + 1*SF8) = 40RU/5ms 144 20 ms 16 Bit/user/10ms 64 Bit/user/10ms 16 Bit/user/10ms Max. 2.0 kbps 41% / 12%
Midamble Interleaving Power control (TPC) TFCI Synchronisation Shift (SS) Inband signalling DCCH Puncturing level at Code rate: 1/3 DCH of the DTCH / ½ DCH of the DCCH
DPCH1
Slide 41
MG3700A-E-F-10
UL RMC 384 kbps Information Data
3840
CRC attachement
3840
DTCH
3840
16
3840
16
Turbo Coding 1/3
[(3840+16)*2]*3=23136
Trellis Termination
23136bit / 20ms
1st Interleaving
3840
3840
3840
16
3840
16
max 80
96
[(3840+16)*2]*3=23136
16
240bit
11580
11580
8
(112+8)*2=240 Convolutional Coding 1/2
24
23160bit / 20ms
23160bit / 20ms
DCCH
112
23136bit / 20ms
24
11580
RF-Segmentation
16
11580
Rate Matching 11580 bit punctured to 6891 bit Puncturing Level: 41% 80 RU = 88 * 80 = 7040 Bits available gross
7040 bit
gross
7040 bit
- TFCI - TPC - SS
- 64 bit - 16 bit - 16 bit
- TFCI - TPC - SS
- 64 bit - 16 bit - 16 bit
- Signalling
53
- Signalling
53
puncturing to
6891 bit
puncturing to
6891 bit
6891
6891
Service Multiplexing
2st Interleaving
6944
Physical Channel Mapping
Slot segmentation
SF=8 4 Timeslots SF=2 4 Timeslots
3520
144 352 144 352 352 144 chips 352 352 144 chips 352 88 chips 88 chips
53
6891
53
6891
6944
64
32
3520
144 352 144 352 352 144 chips 352 352 144 chips 352 88 chips 88 chips
6944
3520
144 352 144 352 352 144 chips 352 352 144 chips 352 88 chips 88 chips
64
32
3520
144 352 144 352 352 144 chips 352 352 144 chips 352 88 chips 88 chips
6944
3520
144 352 144 352 352 144 chips 352 352 144 chips 352 88 chips 88 chips
Puncturing Level: 12% Rate Matching (212)
6891
53
6891
6944
144 144 144 144 84 4 144 4 4 80 84 4 144 4 4 80 84 4 144 4 4 80 84 4 144 4 4 80 144 84 4 144 84 4 144 84 4 144 84 44 144 chips 4 4 chips 4 4 chips 4 4 chips 4 4 84 chips 4 4 84 4 144 84 4 144 84 4 144 chips 4 4 chips 4 4 chips 4 4 348 4 chips 4 4 348 4 chips 4 4 348 4 chips 4 4 348 4 chips 4 4 chips chips chips chips TFCI
53
53
53
53
53
6944
64
32
3520
144 352 144 352 352 144 chips 352 352 144 chips 352 88 chips 88 chips
6944
3520
144 352 144 352 352 144 chips 352 352 144 chips 352 88 chips 88 chips
64
32
3520
144 352 144 352 352 144 chips 352 352 144 chips 352 88 88 chips chips
144 144 144 144 84 4 144 4 4 80 84 4 144 4 4 80 84 4 144 4 4 80 84 4 144 4 4 80 144 144 144 144 84 84 44 144 84 44 144 84 44 144 chips 4 4 chips 4 4 chips 4 4 chips 4 4 84 84 84 84 44 144 chips 4 4 chips 4 4 chips 4 4 chips 4 4 348 4 chips 4 4 348 4 chips 4 4 348 4 chips 4 4 348 4 chips 4 4 chips chips chips chips
TFCI TPC & SS
Sub Frame #1
MG3700A-E-F-10
6891
6891
6944
TFCI, TPC and SS
11580 bit punctured to 6891 bit Puncturing Level: 41% 80 RU = 88 * 80 = 7040 Bits available
Sub Frame #2
Sub Frame #3
Sub Frame #4
Sub Frame #5
Sub Frame #6
Sub Frame #7
Sub Frame #8
Slide 42
21
UL RMC Parameters Marker 1
Frame clock
Marker 2
Subframe clock
Marker 3
RF gate
RMS for single phase of IQ
1157 I 2 + Q 2 = 320 mV
IQ output level
Marker
MG3700A-E-F-10
Slide 43
AWGN • • •
AWGN (Additive White Gaussian Noise) simulates interference from other cells. The minimum bandwidth of the AWGN interferer is 1.5 times the chip rate: 1.92 MHz = 1.5 × 1.28 Mcps The flatness across this minimum bandwidth is within ±0.5 dB, and the peak to average ratio at a probability of 0.001% exceeds 10 dB.
MG3700A-E-F-10
22
Slide 44
AWGN
Setup IQproducer Any one
10.5471 dB
Slide 45
MG3700A-E-F-10
BER Test •
Received DTCH data
•
Clock
Setup Example
» PN9 » Rise • Data • Clock
» Fall • Data • Clock
• •
Measuring bit/time Automatic re-synchronization » On – Sync Loss detected
» Off – Sync Loss ignored
MG3700A-E-F-10
Slide 46
23
Demodulation of DCH in Multipath Fading Conditions Test Setup Example Start trigger Wanted Signal Generator MG3700A
Reference clock
Fading Simulator Terminator (MP752A)
AWGN Generator MG3700A
Combiner (MA1612A)
– Start trigger • Front panel [Start/Frame Trigger] Input – 40 ms × n clock
– Reference clock Use only one. • Rear panel [Baseband Ref Clock] Input – 1.28 MHz, 2 × 1.28 MHz (2.56 MHz), 4 × 1.28 MHz (5.12 MHz)
• Rear panel [10MHz/5MHz Ref] Input
– Controller • Makes receivable state for UL RMC by FTM (Factory Test Mode) control • Reports internal BLER calculation for received DTCH
Slide 47
MG3700A-E-F-10
AWGN •
Setup Example
AWGN » Ioc [dBm/1.28MHz]
MG3700A-E-F-10
24
Slide 48
Controller
Transmit Intermodulation Test Setup Example Start trigger
Reference clock
Interference Signal Generator MG3700A Controller
Circulator Spectrum Analyzer
– Start trigger • Front panel [Start/Frame Trigger] Input – 40 ms × n clock
– Reference clock Use only one. • Rear panel [Baseband Ref Clock] Input – 1.28 MHz, 2 × 1.28 MHz (2.56 MHz), 4 × 1.28 MHz (5.12 MHz)
• Rear panel [10MHz/5MHz Ref] Input
– Controller • Makes maximum transmitting power state by FTM (Factory Test Mode) control Slide 49
MG3700A-E-F-10
Interference Signal Setup Example The interference signal is modulated like the BS transmitted signal, and the active time slots of both signals are synchronized. Table 6.38A: Parameters of the BS transmitted signal for transmit intermodulation testing for 1,28 Mcps TDD Parameter TDD Duty Cycle Time slots under test BS output power setting Number of DPCH in each time slot under test Power of each DPCH Data content of DPCH
Value/description TS i; I = 0, 1, 2, 3, 4, 5, 6: transmit, if i is 0,4,5,6; receive, if i is 1,2,3. TS4, TS5 and TS6 PRAT 8 1/8 of Base Station output power real life (sufficient irregular)
» Set LPF from Auto (3 MHz) to 1 MHz. – To improve ACLR
MG3700A-E-F-10
Slide 50
25
UE Test 3GPP 7 8 9
TS 25.102 (Release 7) Receiver Performance requirement Performance requirements (HSDPA) Test
7.3 7.4 7.5 7.6
TS 34.122 (Release 5) 6 Receiver 7 Performance requirements 9 Performance requirements for HSDPA Wanted Interference Signal Signal Generator Generator with BERT
Reference sensitivity level Maximum input level Adjacent Channel Selectivity (ACS) Blocking characteristics In-band blocking
CW AWGN Others Generator Generator
* * MA1612A
MG3692B
Out of band blocking
3 GHz Combiner
20 GHz
MG3700A 7.7 Spurious response 7.8 Intermodulation characteristics * 8.2 Demodulation in static propagation conditions Demodulation of DCH in multi-path fading conditions 8.3 9.2.1 HS-DSCH throughput for Fixed Reference Channels 9.2.3 Reporting of HS-DSCH Channel Quality Indicator 9.2.4 HS-SCCH Detection Performance * : MG3700A for the wanted signal generator generates two signals with interference signal, CW or AWGN.
MA1612A
MG3692B
3 GHz Combiner
20 GHz
* MA1612A
MG3700A
3 GHz Combiner
Fading simulator
Unsupported interference signal pattern Unsupported HSPA
Slide 51
MG3700A-E-F-10
Receiver Test Setup Example Wanted Signal Generator (+ Interference Signal Generator) (+ CW Generator) (+ AWGN Generator) BER Tester MG3700A
Received DTCH data Clock
CW Generator (MG3692B)
6
9
# 0
3
5
8
2
4
7
1
Terminator (MP752A)
*
Controller
Combiner (MA1612A)
– Controller • Makes receivable state for DL RMC by FTM (Factory Test Mode) control • Reports internal BLER calculation for received DTCH
MG3700A-E-F-10
26
Slide 52
Scrambling Code Synchronization Setup Example •
Scrambling code » Each basic midamble code is associated with a cell-specific complex scrambling code. – Created from 16-bit long complex scrambling sequences
» Applies to scrambling (spreading)
•
Set the scrambling code and basic midamble code to UE. – 0 Code Group
Associated Codes
Group 1
SYNC-DL ID 0
SYNC-UL ID 0...7
Group 2
1
8...15
Group 32
31
248...255
Scrambling Code ID 0 1 2 3 4 5 6 7 . . .
Basic Midamble Code ID 0 1 2 3 4 5 6 7
124 125 126 127
124 125 126 127
Slide 53
MG3700A-E-F-10
Wanted Signal Setup Example Test – Receiver excluding Maximum input level
•
DL RMC 12.2 kbps
Setting power level is the Mean power.
Mean power is the power in a bandwidth of at least (1+α) times 1.28 MHz chip rate. The measurement period is a transmit timeslot excluding the guard period. RRC filtered mean power is the power measured through a root raised cosine filter with roll-off α=0.22 and 1.28 MHz chip rate bandwidth. For a perfectly modulated signal, RRC filtered mean power = Mean power - 0.246 dB
MG3700A-E-F-10
Slide 54
27
Wanted Signal Setup Example Test – Maximum input level
•
DL RMC 12.2 kbps – DPCHo multiplexing
Setting power level is the Mean power.
Mean power is the power in a bandwidth of at least (1+α) times 1.28 MHz chip rate. The measurement period is a transmit timeslot excluding the guard period. RRC filtered mean power is the power measured through a root raised cosine filter with roll-off α=0.22 and 1.28 MHz chip rate bandwidth. For a perfectly modulated signal, RRC filtered mean power = Mean power - 0.246 dB
Slide 55
MG3700A-E-F-10
Wanted Signal + Interference Signal Setup Example Test – ACS – Blocking characteristics – Intermodulation characteristics
•
DL RMC 12.2 kbps +
•
Interferer
ACS: 1.6 MHz offset Blocking: 3.2 & 4.8 MHz offset Intermodulation:6.4 MHz offset
» Set Frequency offset – -31.9872 ∼ +31.9872 MHz
MG3700A-E-F-10
28
Slide 56
Unsupported interference signal pattern
Interference Signal The Interference signal is equivalent to a continuous wideband CDMA signal with one code of chip frequency 1.28 Mcps, filtered by an RRC transmit pulse-shaping filter with roll-off α = 0.22.
Slide 57
MG3700A-E-F-10
Wanted Signal + AWGN Setup Example Test – Performance requirements
•
DL RMC 12.2 kbps – DPCHo multiplexing
•
DL RMC 64 kbps
•
DL RMC 144 kbps
•
DL RMC 384 kbps
•
AWGN
– DPCHo multiplexing – DPCHo multiplexing
+
» Ioc [dBm/1.28MHz]
Test Number 1 2 3 4
MG3700A-E-F-10
Iˆor [dB] I oc
BLER
3.6 2.4 2.7 2.8 3.2 3.2
10 -1 10 -2 10 -1 10 -2 10 -1 10
A/B Set
A level
B level
RF level
A
Variable
Static
Coupled
B
Static
Variable
Coupled
Constant
Variable
Variable
Static
-2
Slide 58
29
DPCHo DPCHo simulates an individual intra-cell interferer that is equivalent to a valid UTRA TDD signal with SF 16, using the same time slot(s) as the wanted signal and applying the same cell-specific scrambling code. Parameters Number of DPCHo Scrambling code and basic midamble code number (see note) DPCH Channelization Codes (see note) DPCHo Channelization Codes (see note)
Unit
Test 1 8 0
Test 2 2 0
Test 3 2 0
Test 4 0 0
C(k,Q)
C(i,16) i=1…8 C(i,16) 9≤ i ≤10 -10
C(i,16) i=1…8 C(i,16) 9≤ i ≤10 -10
C(i,16) i=1…10 -
64
144
384
DPCH o _ E c I or
DB
C(i,16) i=1,2 C(i,16) 3≤ i ≤10 -10
Ioc Information Data Rate
dBm/1,28MHz Kbps
12.2
C(k,Q)
0
-60
Slide 59
MG3700A-E-F-10
DL RMC 12.2 kbps
DPCH
Parameter Information data rate RU's allocated
Value 12,2 kbps 1TS (2*SF16) 2RU/5ms Midamble 144 Interleaving 20 ms Power control (TPC) 4 Bit/user/10ms TFCI 16 Bit/user/10ms Synchronisation Shift (SS) 4 Bit/user/10ms Inband signalling DCCH 2.4 kbps Puncturing level at Code rate 1/3 : DCH of the 33% / 33% DTCH / DCH of the DCCH
P-CCPCH
MG3700A-E-F-10
30
Slide 60
=
DPCH DPCHo
DL RMC 12.2 kbps MAC-Header
Information Data
DTCH
244
244
CRC attachement
16
4
244
260bit/20ms
Tail bit attachement
244
8
16
8
12
112
(260+8)*3=804
804bit/20ms
1st Interleaving
402
8
(112+8)*3=360
804bit/20ms
402
RF-Segmentation
DCCH
100
260bit/20ms
(260+8)*3=804
Conv. Coding 1/3
96
360bit
402
402
Rate Matching 402 bit puncturing to 268 bit Puncturing Level: 33% 4 RU = 88 * 4 = 352 Bits available gross
352 bit
gross
352 bit
- TFCI - TPC - SS
- 16 bit - 4 bit - 4 bit
- TFCI - TPC - SS
- 16 bit - 4 bit - 4 bit
- Signalling
- 60 bit
- Signalling
- 60 bit
puncturing to
268 bit
puncturing to
268 bit
268
60
328
TFCI, TPC and SS
SF=16 SF=16
144
44
40
chips
4
16
TFCI
8
44
268
144
44
40
chips
4
16
176
44
144 4 4 36 chips
144
44
40
chips
4
8
44
144 4 4 36 chips
60
328
176
144
44
40
chips
4
44
144
44
40
chips
4
268
16
8
44
60
60
60
60
328
176
144 4 4 36 chips
60
328
176
144 4 4 36 chips
Puncturing Level: 33% Rate Matching (240)
268
328
328
176
144 4 4 36 chips
60
328
176
Physical Channel Mapping
268
268
328
2st Interleaving
Slot segmentation
268
268
Service Multiplexing
402 bit puncturing to 268 bit Puncturing Level: 33% 4 RU = 88 * 4 = 352 Bits available
144
44
40
chips
4
16
176
44
144 4 4 36 chips
144
44
40
chips
4
8
176
44
144 4 4 36 chips
144
44
40
chips
4
44
144 4 4 36 chips
TFCI TPC & SS
Sub Frame #1
Sub Frame #2
Sub Frame #3
Sub Frame #4
Sub Frame #5
Sub Frame #6
Sub Frame #7
Sub Frame #8
Slide 61
MG3700A-E-F-10
DL RMC 64 kbps
DPCH DPCHo Parameter Information data rate RU's allocated Midamble Interleaving Power control (TPC) TFCI Synchronisation Shift (SS) Inband signalling DCCH Puncturing level at Code rate: 1/3 DCH of the DTCH/ ½ DCH of the DCCH
MG3700A-E-F-10
Value
64 kbps 1TS (8*SF16) = 8RU/5ms 144 20 ms 4 Bit/user/10ms 16 Bit/user/10ms 4 Bit/user/10ms 2.4 kbps 32% / 0
Slide 62
31
DL RMC 64 kbps MAC-Header
Information Data
1280
CRC attachement
1280
DTCH 16
Turbo Coding 1/3
[(640*2)+16]*3=3888
Trellis Termination
3888bit / 20ms
1st Interleaving
4
1280
1280
16
12
112
3888bit / 20ms
3900bit / 20ms
1950
8
(112+8)*2=240 Convolutional Coding 1/2
12
3900bit / 20ms
1950
RF-Segmentation
DCCH
100
[(640*2)+16]*3=3888
12
96
240bit
1950
1950
Rate Matching 1950 bit punctured to 1324 bit Puncturing Level: 32% 16 RU = 88 * 16 = 1408 Bits available gross
1408 bit
gross
1408 bit
- TFCI - TPC - SS
- 16 bit - 4 bit - 4 bit
- TFCI - TPC - SS
- 16 bit - 4 bit - 4 bit
- Signalling
- 60 bit
- Signalling
- 60 bit
puncturing to
1324 bit
puncturing to
1324 bit
1324
60
1384
TFCI, TPC and SS
SF=16 SF=16 SF=16 SF=16 SF=16 SF=16 SF=16 SF=16
16
44 44 44
Sub Frame #1
8
1384
704
144 44 chips 144 44 chips 144 44 chips 144 44 chips 144 44 44 chips 144 44 44 chips 144 44 44 chips 144 40 4 4 4 36 chips TFCI TFCI TPC & SS 44
60
144 chips 144 chips 144 chips 144 chips 144 44 chips 144 44 chips 144 44 chips 144 40 4 4 chips 44
44
44
44
44
44
44
44
16
44 44 44 4 36
Sub Frame #2
144 chips 144 chips 144 chips 144 chips 144 44 chips 144 44 chips 144 44 chips 144 40 4 4 chips
8
1384
704
44
44
44
44
44
44
44
44 44 44 44 4 36
Sub Frame #3
60
144 chips 144 chips 144 chips 144 chips 144 44 chips 144 44 chips 144 44 chips 144 40 4 4 chips
44
44
44
44
44
44
44
16
44 44 44 4 36
Sub Frame #4
144 chips 144 chips 144 chips 144 chips 144 44 chips 144 44 chips 144 44 chips 144 40 4 4 chips
8
44
44
44
44
44
44
44 44 44 44 4 36
Sub Frame #5
60
60
1384
704
44
60
1384
704
44
60
1324
1384
704
Puncturing Level: 0%
1324
1324
1384
704
Physical Channel Mapping
1324
1324
1384
2st Interleaving
Slot segmentation
1324
1324
Service Multiplexing
1950 bit punctured to 1324 bit Puncturing Level: 32% 16 RU = 88 * 16 = 1408 Bits available
144 chips 144 chips 144 chips 144 chips 144 44 chips 144 44 chips 144 44 chips 144 40 4 4 chips
16
704
44
44
44
44
44
44
44
44 44 44 44 4 36
Sub Frame #6
144 chips 144 chips 144 chips 144 chips 144 44 chips 144 44 chips 144 44 chips 144 40 4 4 chips
8
704
44
44
44
44
44
44
44
44 44 44 44 4 36
Sub Frame #7
144 chips 144 chips 144 chips 144 chips 144 44 chips 144 44 chips 144 44 chips 144 40 4 4 chips 44
44
44
44
44
44
44
44 44 44 44 4 36
Sub Frame #8
Slide 63
MG3700A-E-F-10
DL RMC 144 kbps
DPCH DPCHo Parameter Information data rate RU's allocated Midamble Interleaving Power control (TPC) TFCI Synchronisation Shift (SS) Inband signalling DCCH Puncturing level at Code rate: 1/3 DCH of the DTCH/ ½ DCH of the DCCH
MG3700A-E-F-10
32
Value 144 kbps 2TS (8*SF16) = 16RU/5ms 144 20 ms 8 Bit/user/10ms 32 Bit/user/10ms 8 Bit/user/10ms 2.4 kbps 38% / 7%
Slide 64
60
DL RMC 144 kbps MAC-Header
Information Data
2880
CRC attachement
2880
DTCH
2880
16
2880
Turbo Coding 1/3
[(1440*2)+16]*3=8688
Trellis Termination
8688bit / 20ms
1st Interleaving
4
16
12
112
8688bit / 20ms
8700bit / 20ms
4350
8
(112+8)*2=240 Convolutional Coding 1/2
12
8700bit / 20ms
4350
RF-Segmentation
DCCH
100
[(1440*2)+16]*3=8688
12
96
240bit
4350
4350
Rate Matching 4350 bit punctured to 2712 bit Puncturing Level: 38% 32 RU = 88 * 32 = 2816 Bits available gross
2816 bit
gross
2816 bit
- TFCI - TPC - SS
- 32 bit - 8 bit - 8 bit
- TFCI - TPC - SS
- 32 bit - 8 bit - 8 bit
- Signalling
- 56 bit
- Signalling
- 56 bit
puncturing to
2712 bit
puncturing to
2712 bit
2712
2712
Service Multiplexing
2768
TFCI, TPC and SS
Physical Channel Mapping
Slot segmentation
2712
56
2712
2768
2st Interleaving
SF=16 * 2 TS SF=16 * 2 TS SF=16 * 2 TS SF=16 * 2 TS SF=16 * 2 TS SF=16 * 2 TS SF=16 * 2 TS SF=16 * 2 TS
4350 bit punctured to 2712 bit Puncturing Level: 38% 32 RU = 88 * 32 = 2816 Bits available
1408
2712
56
2712
2768
32
2768
16
1408
1408
2712
56
2712
2768
32
2768
16
1408
1408
Puncturing Level: 7% Rate Matching (224)
56
32
16
1408
2768
1408
32
16
1408
144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 44 144 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 40 4 144 4 44 36 40 4 chips 4 36 chips
144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 44 144 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 40 4 144 4 44 36 40 4 chips 4 36 chips
144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 44 144 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 40 4 144 4 44 36 40 4 chips 4 36 chips
144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 44 144 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 40 4 144 4 44 36 40 4 chips 4 36 chips
144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 44 144 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 40 4 144 4 44 36 40 4 chips 4 36 chips
144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 44 144 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 40 4 144 4 44 36 40 4 chips 4 36 chips
Sub Frame #1
Sub Frame #2
Sub Frame #3
Sub Frame #4
Sub Frame #5
Sub Frame #6
Sub Frame #7
Sub Frame #8
44 44 44 44
44 44 44 44 44 44 44 44
44 44 44 44 44 44 44 44
44 44 44 44 44 44 44 44
44 44 44 44 44 44 44 44
56
56
144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 44 144 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 40 4 144 4 44 36 40 4 chips 4 36 chips
44 44
56
2768
144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 144 44 chips 44 chips 144 44 144 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 144 44 44 44 chips 44 chips 144 40 4 144 4 44 36 40 4 chips 4 36 chips 44 44
56
44 44 44 44 44 44 44 44
44 44 44 44 44 44 44 44
44 44 44 44 44 44 44 44
Slide 65
MG3700A-E-F-10
DL RMC 384 kbps
DPCH Parameter Information data rate RU's allocated
Value 384 kbps 4TS (10*SF16) 40RU/5ms Midamble 144 Interleaving 20 ms Power control (TPC) 16 Bit/user/10ms TFCI 64 Bit/user/10ms Synchronisation Shift (SS) 16 Bit/user/10ms Inband signalling DCCH max.2 kbps Puncturing level at Code rate: 1/3 DCH of the 41% / 12% DTCH/ ½ DCH of the DCCH
MG3700A-E-F-10
=
Slide 66
33
DL RMC 384 kbps Information Data
3840
CRC attachement
3840
DTCH
3840
16
3840
16
Turbo Coding 1/3
[(3840+16)*2]*3=23136
Trellis Termination
23136bit / 20ms
1st Interleaving
3840
3840
3840
16
3840
max 80
16
96
[(3840+16)*2]*3=23136
24
16
8
(112+8)*2=240 Convolutional Coding 1/2
24
23160bit / 20ms
11580
DCCH
112
23136bit / 20ms
23160bit / 20ms
11580
RF-Segmentation
16
240bit
11580
11580
Rate Matching 11580 bit punctured to 6891 bit Puncturing Level: 41% 80 RU = 88 * 80 = 7040 Bits available gross
7040 bit
gross
7040 bit
- TFCI - TPC - SS
- 64 bit - 16 bit - 16 bit
- TFCI - TPC - SS
- 64 bit - 16 bit - 16 bit
- Signalling
53
- Signalling
53
puncturing to
6891 bit
puncturing to
6891 bit
6891
6891
Service Multiplexing
2st Interleaving
6944
Physical Channel Mapping
Slot segmentation
6891
53
6891
6944
TFCI, TPC and SS
SF=16 * 4 TS SF=16 * 4 TS SF=16 * 4 TS SF=16 * 4 TS SF=16 * 4 TS SF=16 * 4 TS SF=16 * 4 TS SF=16 * 4 TS SF=16 * 4 TS SF=16 * 4 TS
11580 bit punctured to 6891 bit Puncturing Level: 41% 80 RU = 88 * 80 = 7040 Bits available
6891
53
6891
6944
64
3520
32
3520
6944
3520
32
3520
Sub Frame #2
Sub Frame #3
6944
3520
44 144c 44 44 144c 44 44 144c 44 44 144c 44 44 144c 44 44 144c 44 44 144c 44 44 144c 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 144c 144c 44 44 44 144c 144c 44 44 44 144c 144c 44 44 44 144c 144c 44 44 44 44 44 44 44 144c 144c 44 44 44 144c 144c 44 44 44 144c 144c 44 44 44 144c 144c 44 44 44 44 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 40 4 144c 44 144c 444 4 36 40 4144c 44 144c 444 4 36 40 4 144c 44 144c 444 4 36 40 4 144c 44 144c 444 4 36 40 4 144c 44 144c 444 4 36 40 4 144c 44 144c 444 4 36 40 4 144c 44 144c 444 4 36 40 4 144c 44 144c 444 4 36 40 4 144c 4 4 36 40 4 144c 4 4 36 40 4 144c 4 4 36 40 4 144c 4 4 36 40 4 144c 4 4 36 40 4 144c 4 4 36 40 4 144c 4 4 36 40 4 144c 4 4 36
Sub Frame #1
6891
53
6891
6944
64
Sub Frame #4
Puncturing Level: 12% Rate Matching (212)
53
53
6944
64
32
3520
6944
3520
64
32
3520
44 144c 44 44 144c 44 44 144c 44 44 144c 44 44 144c 44 44 144c 44 44 144c 44 44 144c 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 144c 144c 44 44 44 144c 144c 44 44 44 144c 144c 44 44 44 144c 144c 44 44 44 44 44 44 44 144c 144c 44 44 44 144c 144c 44 44 44 144c 144c 44 44 44 144c 144c 44 44 44 44 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 44 44 144c 144c 44 44 40 4 144c 44 144c 444 4 36 40 4 144c 44 144c 444 4 36 40 4 144c 44 144c 444 4 36 40 4144c 44 144c 444 4 36 40 4 144c 44 144c 444 4 36 40 4 144c 44 144c 444 4 36 40 4 144c 44 144c 444 4 36 40 4144c 44 144c 444 4 36 40 4 144c 4 4 36 40 4 144c 4 4 36 40 4 144c 4 4 36 40 4 144c 4 4 36 40 4 144c 4 4 36 40 4 144c 4 4 36 40 4 144c 4 4 36 40 4 144c 4 4 36
Sub Frame #5
Sub Frame #6
Sub Frame #7
Sub Frame #8
Slide 67
MG3700A-E-F-10
DL RMC Parameters Marker 1
Frame clock
Marker 2
Subframe clock
Marker 3
RF gate
RMS for single phase of IQ
Marker
MG3700A-E-F-10
34
1157 I 2 + Q 2 = 320 mV
IQ output level
Slide 68
53
53
53
AWGN • • •
AWGN (Additive White Gaussian Noise) simulates interference from other cells. The minimum bandwidth of the AWGN interferer is 1.5 times the chip rate (1.92 MHz = 1.5 × 1.28 Mcps). The flatness across this minimum bandwidth is within ±0.5 dB, and the peak to average ratio at a probability of 0.001% exceeds 10 dB.
Slide 69
MG3700A-E-F-10
AWGN
Setup IQproducer Any one
10.5471 dB
MG3700A-E-F-10
Slide 70
35
BER Test •
Setup Example
Received DTCH data » PN9
•
Clock » Rise • Data • Clock
» Fall • Data • Clock
• •
Measuring bit/time Automatic re-synchronization » On – Sync Loss detected
» Off – Sync Loss ignored
Slide 71
MG3700A-E-F-10
Demodulation of DCH in Multipath Fading Conditions Test Setup Example Wanted Signal Generator MG3700A
Fading Simulator
AWGN Generator MG3700A
6
9
# 0
3
5
8
2
4
7
1
*
Terminator (MP752A)
Controller
Combiner (MA1612A)
– Controller • Makes receivable state for DL RMC by FTM (Factory Test Mode) control • Reports internal BLER calculation for received DTCH
MG3700A-E-F-10
36
Slide 72
AWGN •
Setup Example
AWGN » Ioc [dBm/1.28MHz]
MG3700A-E-F-10
Slide 73
Additional Information • BS Transmitted Signal for BS Transmitter Test – Explore 3GPP TS 25.142
• UL RMC for UE Transmitter Test
75 89
– Explore 3GPP TS 34.122
MG3700A-E-F-10
Slide 74
37
BS Transmitted Signal for BS Transmitter Test Test – Maximum output power – Transmit ON/OFF time mask – OBW – Spectrum emission mask – ACLR – Spurious emissions – Transmit intermodulation
•
DL 8 DPCH Parameter TDD Duty Cycle Time slots under test BS output power setting Number of DPCH in each time slot under test Power of each DPCH Data content of DPCH
Value/description TS i; i = 0, 1, 2, 3, 4, 5, 6: transmit, if i is 0,4,5,6; receive, if i is 1,2,3. TS4, TS5 and TS6 PRAT 8 1/8 of Base Station output power real life (sufficient irregular)
PRAT: Rated output power of BS It is the mean power level per carrier that the manufacturer has declared to be available at the antenna connector.
MG3700A-E-F-10
Slide 75
DL 8 DPCH
-65 dB -71 dB
MG3700A-E-F-10
38
Slide 76
MS2781A Signature
BS Transmitted Signal for BS Transmitter Test Test – Frequency stability – Minimum output power – EVM (at Pmax –30 dB)
•
DL 1 DPCH Parameter TDD Duty Cycle Time slots under test Number of DPCH in eachtime slot under test BS output power setting Data content of DPCH
Value/description TS i; i = 0, 1, 2, ..., 6: transmit, if i is 0, 4,5,6; receive, if i is 1,2,3. TS4, TS5 and TS6 1 PRAT real life (sufficient irregular)
PRAT: Rated output power of BS It is the mean power level per carrier that the manufacturer has declared to be available at the antenna connector.
MG3700A-E-F-10
Slide 77
DL 1 DPCH
MG3700A-E-F-10
Slide 78
39
BS Transmitted Signal for BS Transmitter Test Test – EVM – PCDE
•
DL 10 DPCH Parameter TDD Duty Cycle Time slots under test BS output power setting Number of DPCH in each time slot under test Power of each DPCH Data content of DPCH Spreading factor
Value/description TS i; i = 0, 1, 2, ..., 6: transmit, if i is 0,4,5,6; receive, if i is 1,2,3. TS4, TS5 and TS6 PRAT 10 1/10 of Base Station output power real life (sufficient irregular) 16
PRAT: Rated output power of BS It is the mean power level per carrier that the manufacturer has declared to be available at the antenna connector.
MG3700A-E-F-10
Slide 79
DL 10 DPCH
MG3700A-E-F-10
40
Slide 80
BS Transmitted Signal for BS Transmitter Test Test – P-CCPCH power – Differential accuracy of P-CCPCH power
•
DL P-CCPCH Parameter TDD Duty Cycle Time slots carrying PCCPCH BS output power setting Relative power of PCCPCH Data content of DPCH
Value/description TS i; i = 0, 1, 2, ..., 6: transmit, if i is 0,4,5,6; receive, if i is 1,2,3. TS 0 PRAT ½ of BS output power real life (sufficient irregular)
PRAT: Rated output power of BS It is the mean power level per carrier that the manufacturer has declared to be available at the antenna connector.
MG3700A-E-F-10
Slide 81
DL P-CCPCH
MG3700A-E-F-10
Slide 82
41
BS Transmitted Signal for BS Transmitter Test Test – Spectrum emission mask – ACLR – Spurious emissions – Transmit intermodulation – EVM – PCDE
•
Unsupported HSPA
DL 8 HS-PDSCH Parameter TDD Duty Cycle Time slots under test BS output power setting HS-PDSCH modulation Number of HS-PDSCH in each time slot under test Power of each HS-PDSCH Data content of HS-PDSCH Spreading factor
Value/description TS i; i = 0, 1, 2, 3, 4, 5, 6: transmit, if i is 0,4,5,6; receive, if i is 1,2,3. TS4, TS5 and TS6 PRAT 16QAM 8 1/8 of Base Station output power real life (sufficient irregular) 16
PRAT: Rated output power of BS It is the mean power level per carrier that the manufacturer has declared to be available at the antenna connector.
MG3700A-E-F-10
Slide 83
BS Transmitted Signal for BS Transmitter Test » Set LPF properly. – To improve ACLR
MG3700A-E-F-10
42
Slide 84
Effect of ACLR on LPF Setting LPF curve image
•
DL 8 DPCH
-64 dB -71 dB
» When LPF changed from Auto (3 MHz) to 1 MHz
-65 dB -71 dB
Slide 85
MG3700A-E-F-10
Effect of EVM on LPF Setting •
DL 10 DPCH
» When LPF changed from Auto (3 MHz) to 1 MHz
MG3700A-E-F-10
Slide 86
43
BS Transmitted Signal for BS Transmitter Test Parameters Marker 1
Frame clock
Marker 2
Subframe clock
Marker 3
RF gate
RMS for single phase of IQ
1157 I 2 + Q 2 = 320 mV
IQ output level
Marker
MG3700A-E-F-10
Slide 87
BS Transmitted Signal for BS Transmitter Test CCDF Simulation Mean power within TS
MG3700A-E-F-10
44
Slide 88
UL RMC for UE Transmitter Test Test – Maximum output power – Frequency stability – Minimum output power – Transmit ON/OFF time mask – OBW – Spectrum emission mask – ACLR – Spurious emissions – Transmit intermodulation – EVM
•
UL RMC 12.2 kbps Parameter UL Reference measurement channel Uplink Power Control
Data content
Value/description 12,2kbps, according to annex C.2.1 SS level and signalling values such that UE transmits maximum power. real life (sufficient irregular)
Slide 89
MG3700A-E-F-10
UL RMC 12.2 kbps
Parameter Information data rate RU's allocated Midamble Interleaving
12,2 kbps 1TS (1*SF8) = 2RU/5ms 144 20 ms
Power control (TPC)
4 Bit/user/10ms
TFCI
16 Bit/user/10ms
Synchronisation Shift (SS)
4 Bit/user/10ms
Inband signalling DCCH Puncturing level at Code rate 1/3: DCH of the DTCH / DCH of the DCCH
MG3700A-E-F-10
2 kbps 33% / 33%
Slide 90
45
UL RMC 12.2 kbps MAC-Header
Information Data
DTCH
244
244
CRC attachement
16
4
244
260bit/20ms
Tail bit attachement
244
8
16
1st Interleaving
8
804bit/20ms
12
112
(260+8)*3=804
402
8
(112+8)*3=360
804bit/20ms
402
RF-Segmentation
DCCH
100
260bit/20ms
(260+8)*3=804
Conv. Coding 1/3
96
360bit
402
402
Rate Matching 402 bit puncturing to 268 bit Puncturing Level: 33% 4 RU = 88 * 4 = 352 Bits available gross
352 bit
gross
352 bit
- TFCI - TPC - SS
- 16 bit - 4 bit - 4 bit
- TFCI - TPC - SS
- 16 bit - 4 bit - 4 bit
- Signalling
- 60 bit
- Signalling
- 60 bit
puncturing to
268 bit
puncturing to
268 bit
268
268
Service Multiplexing
328
176
Physical Channel Mapping
Slot segmentation
SF=8
84 4 144 4 4 80 chips
TFCI
60
268
268
60
268
328
16
8
176
84 4 144 4 4 80 chips
328
176
84 4 144 4 4 80 chips
268
60
268
328
16
8
176
328
176
84 4 144 4 4 80 chips
84 4 144 4 4 80 chips
Puncturing Level: 33% Rate Matching (240)
60
60
328
16
8
176
84 4 144 4 4 80 chips
328
176
84 4 144 4 4 80 chips
16
8
176
84 4 144 4 4 80 chips
TFCI TPC & SS
Sub Frame #1
MG3700A-E-F-10
268
328
2st Interleaving
TFCI, TPC and SS
402 bit puncturing to 268 bit Puncturing Level: 33% 4 RU = 88 * 4 = 352 Bits available
Sub Frame #2
Sub Frame #3
Sub Frame #4
Sub Frame #5
Sub Frame #6
Sub Frame #7
Sub Frame #8
Slide 91
UL RMC 12.2 kbps
MG3700A-E-F-10
46
Slide 92
60
60
60
UL RMC for UE Transmitter Test Test – Maximum output power – PCDE
•
UL RMC multicode 12.2 kbps Parameter Reference measurement channel Uplink Power Control
Data content
Unsupported signal pattern
Value/description Multicode 12,2 kbps, according to annex C.2.2.2 SS level and signalling values such that UE transmits maximum power real life (sufficient irregular)
Slide 93
MG3700A-E-F-10
UL RMC Multicode 12.2 kbps
Unsupported signal pattern
Parameter Information data rate RU's allocated
Value 12,2 kbps 1TS (2*SF16) 2RU/5ms Midamble 144 Interleaving 20 ms Power control (TPC) 4 Bit/user/10ms TFCI 16 Bit/user/10ms 4 Bit reserved for future use (place of SS) 4 Bit/user/10ms Inband signalling DCCH 2.4 kbps Puncturing level at Code rate 1/3: DCH of the 33% / 33% DTCH / DCH of the DCCH
MG3700A-E-F-10
=
Slide 94
47
UL RMC Multicode 12.2 kbps MAC-Header
Information Data
DTCH
244
244
CRC attachement
16
244
260bit/20ms
Tail bit attachement
4
244
8
16
12
112
402
8
(112+8)*3=360
804bit/20ms
402
RF-Segmentation
8
(260+8)*3=804
804bit/20ms
1st Interleaving
DCCH
100
260bit/20ms
(260+8)*3=804
Conv. Coding 1/3
96
360bit
402
402
Rate Matching 402 bit puncturing to 268 bit Puncturing Level: 33% 4 RU = 88 * 4 = 352 Bits available gross
352 bit
gross
352 bit
- TFCI - TPC - Reserved
- 16 bit - 4 bit - 4 bit
- TFCI - TPC - Reserved
- 16 bit - 4 bit - 4 bit
- Signalling
- 60 bit
- Signalling
- 60 bit
puncturing to
268 bit
puncturing to
268 bit
268
60
328
TFCI, TPC and SS
SF=16 SF=16
144 chips
44
40
4
16
TFCI
8
328
176
44
144 4 4 36 chips
60
144 chips
44
40
4
44
144 4 4 36 chips
144 chips
44
40
4
16
8
328
176
44
144 4 4 36 chips
60
144 chips
44
40
4
44
144 chips
44
40
4
16
8
44
60
60
60
328
176
144 4 4 36 chips
60
328
176
144 4 4 36 chips
60
268
328
176
Puncturing Level: 33% Rate Matching (240)
268
268
328
176
Physical Channel Mapping
268
268
328
2st Interleaving
Slot segmentation
268
268
Service Multiplexing
402 bit puncturing to 268 bit Puncturing Level: 33% 4 RU = 88 * 4 = 352 Bits available
144 chips
44
40
4
16
176
44
144 4 4 36 chips
144 chips
44
40
4
8
176
44
144 4 4 36 chips
144 chips
44
40
4
44
144 4 4 36 chips
TFCI TPC & Reserved
Sub Frame #1
Sub Frame #2
MG3700A-E-F-10
Sub Frame #3
Sub Frame #4
Sub Frame #5
Sub Frame #6
Sub Frame #7
Sub Frame #8
Slide 95
UL RMC for UE Transmitter Test » Set LPF properly. – To improve ACLR
MG3700A-E-F-10
48
Slide 96
Effect of ACLR on LPF Setting LPF curve image
•
UL RMC 12.2 kbps
-63 dB -68 dB
» When LPF changed from Auto (3 MHz) to 1 MHz
-64 dB -69 dB
Slide 97
MG3700A-E-F-10
Effect of EVM on LPF Setting •
UL RMC 12.2 kbps
» When LPF changed from Auto (3 MHz) to 1 MHz
MG3700A-E-F-10
Slide 98
49
UL RMC for UE Transmitter Test Parameters Marker 1
Frame clock
Marker 2
Subframe clock
Marker 3
RF gate
RMS for single phase of IQ
1157 I 2 + Q 2 = 320 mV
IQ output level
Marker
MG3700A-E-F-10
Slide 99
UL RMC for UE Transmitter Test CCDF Simulation Mean power within TS
MG3700A-E-F-10
50
Slide 100
Specifications are subject to change without notice.
Anritsu Corporation 5-1-1 Onna, Atsugi-shi, Kanagawa, 243-8555 Japan Phone: +81-46-223-1111 Fax: +81-46-296-1264
• U.S.A.
Anritsu Company 1155 East Collins Blvd., Suite 100, Richardson, TX 75081, U.S.A. Toll Free: 1-800-267-4878 Phone: +1- 972-644-1777 Fax: +1-972-671-1877
• Canada Anritsu Electronics Ltd.
700 Silver Seven Road, Suite 120, Kanata, Ontario K2V 1C3, Canada Phone: +1-613-591-2003 Fax: +1-613-591-1006
• Brazil
Anritsu Eletrônica Ltda. Praca Amadeu Amaral, 27 - 1 Andar 01327-010-Paraiso-São Paulo-Brazil Phone: +55-11-3283-2511 Fax: +55-11-3288-6940
• U.K.
Anritsu EMEA Ltd. 200 Capability Green, Luton, Bedfordshire, LU1 3LU, U.K. Phone: +44-1582-433200 Fax: +44-1582-731303
• France Anritsu S.A.
9 Avenue du Québec, Z.A. de Courtabœuf 91951 Les Ulis Cedex, France Phone: +33-1-60-92-15-50 Fax: +33-1-64-46-10-65
• Germany Anritsu GmbH
Nemetschek Haus, Konrad-Zuse-Platz 1 81829 München, Germany Phone: +49-89-442308-0 Fax: +49-89-442308-55
• Italy
Anritsu S.p.A.
Via Elio Vittorini 129, 00144 Roma, Italy Phone: +39-6-509-9711 Fax: +39-6-502-2425
• Sweden
Anritsu AB
Borgafjordsgatan 13, 164 40 KISTA, Sweden Phone: +46-8-534-707-00 Fax: +46-8-534-707-30
• Finland
Anritsu AB
Teknobulevardi 3-5, FI-01530 VANTAA, Finland Phone: +358-20-741-8100 Fax: +358-20-741-8111
• Denmark
• India Anritsu Pte. Ltd. India Branch Office Unit No. S-3, Second Floor, Esteem Red Cross Bhavan, No. 26, Race Course Road, Bangalore 560 001, India Phone: +91-80-32944707 Fax: +91-80-22356648
• P.R. China (Hong Kong) Anritsu Company Ltd.
Units 4 & 5, 28th Floor, Greenfield Tower, Concordia Plaza, No. 1 Science Museum Road, Tsim Sha Tsui East, Kowloon, Hong Kong Phone: +852-2301-4980 Fax: +852-2301-3545
• P.R. China (Beijing)
Anritsu Company Ltd. Beijing Representative Office
Anritsu A/S
Kirkebjerg Allé 90, DK-2605 Brøndby, Denmark Phone: +45-72112200 Fax: +45-72112210
• Spain
Room 1515, Beijing Fortune Building, No. 5, Dong-San-Huan Bei Road, Chao-Yang District, Beijing 10004, P.R. China Phone: +86-10-6590-9230 Fax: +86-10-6590-9235
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8F Hyunjuk Building, 832-41, Yeoksam Dong, Kangnam-ku, Seoul, 135-080, Korea Phone: +82-2-553-6603 Fax: +82-2-553-6604
Anritsu EMEA Ltd. Oficina de Representación en España
• United Arab Emirates
• Korea
Anritsu Corporation, Ltd.
• Australia
Anritsu Pty. Ltd.
Anritsu EMEA Ltd. Dubai Liaison Office
Unit 21/270 Ferntree Gully Road, Notting Hill, Victoria 3168, Australia Phone: +61-3-9558-8177 Fax: +61-3-9558-8255
P O Box 500413 - Dubai Internet City Al Thuraya Building, Tower 1, Suit 701, 7th Floor Dubai, United Arab Emirates Phone: +971-4-3670352 Fax: +971-4-3688460
• Taiwan Anritsu Company Inc.
Anritsu Pte. Ltd.
7F, No. 316, Sec. 1, Neihu Rd., Taipei 114, Taiwan Phone: +886-2-8751-1816 Fax: +886-2-8751-1817
• Singapore
10, Hoe Chiang Road, #07-01/02, Keppel Towers, Singapore 089315 Phone: +65-6282-2400 Fax: +65-6282-2533
Please Contact:
070207 Printed on 70% Recycled Paper
No. MG3700A-E-F-10-(2.00)
Printed in Japan
2007-3
AKD
