Annual Report 2005 Solid-State Electronics Department Prof.Dr.rer.nat. F.J.Tegude
Universität Duisburg-Essen Fakultät für Ingenieurwissenschaften Institut für Technologien der Informationstechnik
Halbleitertechnik/Halbleitertechnologie
Lotharstrasse 55 / ZHO D-47057 Duisburg Germany Tel.: Fax:
++49 (0)203 379 3392 (Secr.) ++49 (0)203 379 3400
email:
[email protected] www:
Editors:
http://www.hlt.uni-duisburg.de
Dr.-Ing. Werner Prost Dr.-Ing. Wolfgang Brockerhoff
Halbleitertechnik/ Halbleitertechnologie
Annual Report 2005 - Solid-State Electronics Department
Table of Contents 1
Preface 1
2
Members of the Department.................................................................................................... 3
3
Teaching Activities ................................................................................................................... 5
4
3.1
Lectures and Laboratory Exercises ................................................................................... 5
3.2
Student Reports and Diploma Thesis................................................................................ 8
3.3
Doctor Thesis .................................................................................................................... 9
3.4
Seminar on Semiconductor Electronics .......................................................................... 10
Research Activities ................................................................................................................. 13 4.1
4.2
4.3
Epitaxial Growth and Materials ...................................................................................... 13 4.1.1
Growth, Processing and Characterisation of optimised GaAsSb DHBTs S. Topaloglu, I. Regolin, H. Barbknecht, A. Osinski ........................................ 14
4.1.2
Influence of Emitter Doping on the Performance of InGaAs/InP-Single Heterostructure Bipolar Transistors J. Driesen .......................................................................................................... 18
4.1.3
On the impact of the Carrier Gas on the MOVPE Growth of In0.53Ga0.47As/InP HBT I. Regolin, S. Topaloglu, S. Neumann, W. Prost, S. Taniguchi, R. Geitmann .. 21
4.1.4
Application of Atomic Hydrogen Source in the Molecular-Beam Epitaxy V. Khorenko, R. Geitmann ................................................................................ 24
Device and Circuit Processing ........................................................................................ 27 4.2.1
Influence of Collector Doping on HBT Performance S. Topaloglu, H. Barbknecht............................................................................. 28
4.2.2
Plasma process for InP-based semiconductors with low etch rates using an ICP-System M. Meier, S. Topaloglu ..................................................................................... 32
4.2.3
Development of pinip-Photodetectors with High Functionality for Digital Circuits A. Poloczek, H. Barbknecht .............................................................................. 36
4.2.4
Realization of High Performance InGaAs pin-diode on Silicon Substrate A. Poloczek........................................................................................................ 39
Device and Circuit Simulation, Measurement and Modelling........................................ 43 4.3.1
Low Temperatur Characterisation of SiGe Resonant Tunneling Diodes A. Matiss, D. Paul ............................................................................................. 44
4.3.2
InP-Heterostructure-Fieldeffect Transistor Parasitics Estimation A. Matiss ........................................................................................................... 47
Annual Report 2005 - Solid-State Electronics Department
4.4
4.3.3
High-Frequency Characterisation and Modelling of HBTs K. Baumann, S. Ehrich...................................................................................... 50
4.3.4
SPICE Simulation of Photo Receiver using PIN-RTD-HBT devices W. Wang, J. Driesen, W. Prost ......................................................................... 53
4.3.5
Optoelectronical High Frequency Characterisation of MOBILE Gates with Optical Input Th. Geistert, A. Matiss ...................................................................................... 56
4.3.6
Software Development based on LabVIEW for DC - and HF - Characterisation of HBT I. Nannen, J. Driesen, S. Ehrich ....................................................................... 59
4.3.7
Development of a program for visualization and analysis of high frequency and direct current measuring data of Hetero-Bipolar-Transistors J. Kalender, J. Driesen ..................................................................................... 63
4.3.8
High Frequency Noise Measurements of Circuits using an Active Noise Source and a Spectrum Analyser R.Tobera, A. Matiss .......................................................................................... 66
4.3.9
Automated Characterisation of Power Amplifiers for 3G-WCDMA Mobile Communication Systems for Evaluating Predistortion Techniques J. Henze, W. Brockerhoff, E. Busheri, A. A. Rezazadeh ................................... 69
4.3.10
Detailed analysis of a fully integrated voltage-controlled differential Colpittsoscillator A.Viessmann, J. Driesen ................................................................................... 73
Nanoelectronics............................................................................................................... 77 4.4.1
Composition Control in MOVPE-Grown InGaAs Nanowhiskers I. Regolin........................................................................................................... 78
4.4.2
GaAs Whiskers Grown by MOVPE Using Fe Nanoparticles I. Regolin........................................................................................................... 81
4.4.3
Fabrication and electrical characteristics of n-InAs single nanowhisker fieldeffect transistors Q. T. Do, I. Regolin........................................................................................... 84
Annual Report 2005 - Solid-State Electronics Department
5
4.5
Conference Contributions ............................................................................................... 87
4.6
Publications..................................................................................................................... 89
4.7
Research Projects ............................................................................................................ 91
4.8
Other Activities ............................................................................................................... 93 4.8.1
DGKK Workshop 2005 W.Prost.............................................................................................................. 94
4.8.2
Excursion 2005 W.Brockerhoff ................................................................................................... 96
Guide to the Solid-State Electronics Department ............................................................... 98
Annual Report 2005 - Solid-State Electronics Department
1
1
Preface
This report presents the teaching and research activities of the Solid State Electronics Department (Fachgebiet Halbleitertechnik/Halbleitertechnolgie) during the year 2005. Our traditional “work horse” devices, i.e. Heterostructure-Fieldeffect-Transistors (HFETs) and Heterostructure-Bipolar-Transistors (HBTs), are increasingly coupled our even merged with devices like pin-photodiodes or Resonant Tunneling Diodes (RTD). The idea is to increase circuit functionality with a minimum count of devices in high speed digital and analog circuits. The concept is demonstrated most distinctively by a pin-RTD-HBT combination serving as a highly compact photo receiver with signal and clock input on two different wavelengths. Another main research direction is to provide III-V-semiconductor performance on a silicon platform. One way is to use the InP-quasi-substrate on Si-substrate approach demonstrated for high quality photodiodes and potentially suited for CMOS and III-V co-integration. A further thrust at our lab for the Si - III-V combination is the III-V-nanowires (“nano-whiskers”) on silicon substrates approach, which has been started one year ago and yielded a broad area of applications. Besides the excellent optical properties with a large variety of possible emission wavelengths, we only recently fabricated an InAs nanowire MISFET with very high transconductance even for insulator thickness of 150nm. Even if an rf-performance demonstration is still far from being realized, this shows up the potential of the nanowire approach.
Finally, I want to thank friends and partners everywhere for their support and cooperation, and last, but not least, all students and members of the Solid State Electronics Department for their efforts and contributions.
Duisburg, April 2006
Prof. Dr. rer. nat. F.-J. Tegude
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Annual Report 2005 - Solid-State Electronics Department
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Annual Report 2005 - Solid-State Electronics Department
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Members and Guests of the Department 379-
office
email
- 3391
LT 207
[email protected]
- 3392
LT 206
[email protected]
Dr.-Ing. Wolfgang Brockerhoff (AOR)
- 2989
LT 205
[email protected]
Dipl.-Phys. Quoc Thai Do
- 3393
LT 106
[email protected]
Dipl.-Ing. Jörn Driesen
- 2491
LT 218
[email protected]
- 3881
LT 204
[email protected]
Dr.-rer.nat. Victor Khorenko
- 3877
LT 104
[email protected]
Dipl.-Ing. Andreas Matiss
- 4605
LT 203
[email protected]
Dipl.-Ing. Artur Poloczek
- 3878
LT 104
[email protected]
Dr.-Ing. Werner Prost
- 4607
LT 205
[email protected]
Dipl.-Ing. Ingo Regolin
- 3877
LT 104
[email protected]
M.Sc. Serkan Topaloglu
- 2492
LT 218
[email protected]
Udo Doerk
- 3395
LT 202
[email protected]
Dipl.-Ing. Ralf Geitmann
- 4604
LT 202
[email protected]
Dipl.-Ing. Wolfgang Molls
- 4603
LT 201
[email protected]
Andrea Osinski
- 4600
LT 104
[email protected]
Ing. (grad.) Reimund Tilders
- 3396
LT 201
[email protected]
Sarah Dohle
- 4095
LT 106
[email protected]
Florian Dippe
- 4618
LT 106
[email protected]
head of the department Prof. Dr.rer.nat. Franz-Josef Tegude secretary Dagmar Birke scientific staff
Dipl.-Ing. Silja Ehrich
until 06/2005
technical staff
apprentices
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Annual Report 2005 - Solid-State Electronics Department
students Kai Baumann
Benedikt Kürten
since 09/05
Yun Chen
since 10/05
Abu Shariha Luay
until 06/05
Thomas Geistert
until 06/05
Matthias Meier
until 03/05
Sven Goßlau
since 09/05
Benjamin Münstermann
since 09/05
Benjamin Hoffmann
Ingo Nannen
Christoph Kandler
Björn Rasmussen
Piotr Kropelnicki André Krowas
until 06/05
Robert Tobera
until 06/05
Annual Report 2005 - Solid-State Electronics Department
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Teaching Activities
3.1
Lectures and Laboratory Exercises
5
Schedule Lectures and exercises
diploma course
Solid-State Electronics 1 Festkörperelektronik 1
3rd sem.
Solid-State Electronics 2 Festkörperelektronik 2
4th sem.
Introduction to Solid-State Electronics Einführung in die Festkörperelektronik Technical Electronics 1 Technische Elektronik 1 / Elektronische Bauelemente
B.Sc.
M.Sc
4th sem. 5th sem. 3rd / 5th sem.
Basic Electronic Devices Grundlagen Elektronischer Bauelemente Technical Electronics 2 Technische Elektronik 2 / Elektronische Schaltungen
International Studies in Engineering (ISE)
6th sem.
Basic Electronic Circuits Grundlagen Elektronischer Schaltungen Semiconductor Microelectronics Technology 1/ III-V Technologies and Components 1/ Halbleitertechnologie 1
2nd sem. optional
Laboratory exercises Communication Electronics Praktikum Technische Elektronik
7th sem.
Introduction to Operational Amplifiers Praktikum Operationsverstärker
6th/8th sem. (optional)
optional
Semiconductor Technology 8th sem. Praktikum Halbleitertechnologie/ Halbleitertechnologie 2 (optional)
optional
Basic Electronic Devices Praktikum Grundlagen Elektronischer Bauelemente Basic Electronic Circuits Praktikum Grundlagen Elektronischer Schaltungen Seminars and Colloquia Seminar on Semiconductor Electronics Probleme der modernen Halbleiterphysik Seminar on Epitaxial Problems
3rd / 5th sem. 2nd sem.
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Annual Report 2005 - Solid-State Electronics Department
Lectures and Exercises: Introduction to Solid-State Electronics / Solid-State Electronics 1,2 (Einführung in die Festkörperelektronik) / (Festkörperelektronik 1,2) These courses start with an introduction to the basics of Quantum physics. Based on Schroedinger's equation and Heisenberg's uncertainty relations a comprehensive understanding of semiconductor band structure is achieved. The first part (Introduction to Solid-State Electronics) also includes carrier statistics and ends up with a discussion of current continuity and Poisson's equation. In the second part of this lecture the basic building blocks of electronic devices, i.e. semiconductor-metal contact, MIS system, pn junction and heterostructures, are treated for subsequent courses on field effect and bipolar electronics.
Basic Electronic Devices (Technische Elektronik 1) MOS-Capacitors, charge coupled devices and Field-Effect Transistors both, on Silicon and III/V material, are treated during the first part of the course. The fundamentals as well as the DC characteristics of MOSFET, MESFET, JFET, and Heterostructure FET (HFET) are derived and analysed in detail. Additionally, bipolar devices - pn-diodes, npn- and pnp-transistors as well as tunnel- and zenerdiodes - are considered. Based on the dc characterisitics simple small-signal equivalent circuits are derived.
Basic Electronic Circuits (Technische Elektronik 2) This course covers the basic methods to calculate complex electronic circuits using the devices treated within the "Basic Electronic Devices". Various device models with respect to circuit design and circuit simulation using commercial circuit simulation tools are discussed. Numerous analog (e.g. operational amplifiers) and digital applications are included.
Semiconductor Microelectronics Technology 1,2 (Halbleitertechnologie 1,2) The semiconductor microelectronics technology lectures are devoted to III/V-semiconductor heterostructures for high speed electronic devices. The process steps from crystal growth to circuit fabrication are discussed. The first semester is focused on heterostructure material issues. Modern growth techniques like molecular beam epitaxy (MBE) and metal-organic vapour-phase epitaxy (MOVPE) are discussed in terms atomic layer control of thickness, composition, and doping. High Resolution X-ray diffraction, photoluminescence, and ellipsometry are explained for nondestructive material assessment in the mono-layer scale. The second semester is devoted to microelectronic fabrication techniques for high speed (f ≥100 GHz) devices and circuits. The lateral and vertical processing of epitaxial films, insulating layers, and metallizations are presented for high performance monolithic high speed analog and digital integrated circuits.
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Laboratory exercises Communication Electronics, Basic Electronic Devices, Basic Electronic Circuits (Praktikum Technische Elektronik) Within the laboratory exercises students apply their theoretical knowledge based on the lectures "Basic Electronic Devices" and "Basic Electronic Circuits". The capacitance-voltage characteristics of schottky diodes are measured and evaluated. The dc and small signal parameters of bipolar transistors as well as the switching behaviour is experimentally investigated. The course also covers the analysis of the dynamical performance of digital circuits. Additionally, numerical simulations and synthesis of basic electronic circuits are carried out on a UNIX system.
Introduction to Operational Amplifiers (Praktikum Operationsverstärker) The aim of this course is the understanding of the basic principles and the characteristics of operational amplifiers (OpAmps). The laboratory exercises demonstrate their applicability in electronic circuits enabling the students to an independent design and understanding of complex circuits. Starting with the measurement and interpretation of the most important characteristic parameters of OpAmps, circuits like adders and multipliers, amplifiers and active filters are intensively calculated and investigated. Oscillators and generators are designed and measured.
Seminars and Colloquia Seminar on Semiconductor Electronics (Probleme der modernen Halbleiterphysik) Within this seminar actual topics of the semiconductor electronics are discussed. Students, but also members of the department, report about their own work.
Seminar on Epitaxial Problems Problems of the epitaxial growth of semiconductor structures are analysed, results are interpreted and future trends are discussed.
Colloquium on Optoelectronics Recent developments and problems in the Optoelectronics/Photonics field and neighboured topics are presented by invited experts from all over the world.
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3.2
Annual Report 2005 - Solid-State Electronics Department
Student Reports and Diploma Thesis (Studien-/Diplomarbeiten)
Student reports PIOTR KROPELNICKI
Skalierungsverhalten messungen
von
Resonanztunnel-Bipolartranistoren
anhand
von
Gleichstrom-
08.01.2005
INGO NANNEN
Entwicklung eines LabView Programms zur DC- und HF-Charakterisierung von HBT 13.01.2005
MATTHIAS MEIER
Plasmaprozess für InP-basierte Halbleiter mit niedrigen Ätzraten in einer Anlage mit induktivgekoppeltem Plasma 03.02.2005
THOMAS GEISTERT
Optoelektronische Hochfrequenzcharakterisierung von MOBILE-Gattern mit optischem Eingang 22.03.2005
KAI BAUMANN
Hochfrequenzcharakterisierung und Modellierung von Heterostruktur-Bipolartransistoren 22.07.2005
JAN KALENDER
Entwicklung eines Programms zur Darstellung und Auswertung von Hochfrequenz- und Gleichstrom-Messdaten an HBT 03.08.2005
ROBERT TOBERA
Hochfrequenzrauschmessungen an Schaltungen mittels aktiver Rauschquelle und eines Spektrumanalysators 23.12.2005
Annual Report 2005 - Solid-State Electronics Department
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Bachelor thesis WEI WANG
SPICE Simulation optischer Empfängerverstärker mit PIN-RTD-HBT Bauelementen 24.06.2005
Diploma thesis ALEXANDER VIESSMANN
Untersuchung eines vollständig integrierten und spannungsgesteuerten differentiellen Colpitts Oszillators für den WLAN Standard 802.11g 08.04.2005
JOHANNES HENZE
Automatische Charakterisierung von 3G-WCDMA Mobiltelefon-Leistungsendstufen zum Test digitaler Vor-Verzerrung 23.12.2005
3.3
Doctor Thesis
WOLFGANG OTTEN
Strukturierung und elektrische Eigenschaften von gasphasen-generierten PbS NanokristallFilmen 06.07.2005
SILJA EHRICH
Rigorose Modellbeschreibung für InP basierte Heterostruktur-Bipolartransistoren 29.07.2005
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3.4
Annual Report 2005 - Solid-State Electronics Department
Seminar on Semiconductor Electronics
13.01.2005 CHRISTOPH PRUSINSKI, REPORT ON THE DIPLOMA THESIS:
'Digitale logische Schaltungen auf Basis von Resonanztunnel-Bipolartransistoren' 20.01.2005 ARTUR POLOCZEK, REPORT ON THE DIPLOMA THESIS:
'Entwicklung von Prozessen zur Reduzierung der parasitären Komponenten von HeterostrukturBipolartransistoren' PIOTR KROPELNICKI, REPORT ON THE STUDENT THESIS:
'Skalierungsverhalten von Resonanztunnel-Bipolartranistoren anhand vonGleichstrommessungen' 27.01.2005 MIRKO ROSTEWITZ, REPORT ON THE DIPLOMA THESIS:
'Konzeption und Aufbau von Mess- und Burn-In-Einrichtungen zur Evaluation von GaN-High Power Feldeffekttransistoren für die Satellitenkommunikation im XBand' INGO NANNEN, REPORT ON THE STUDENT THESIS:
'Entwicklung eines LabView Programms zur DC- und HF-Charakterisierung von HBT' 17.03.2005 MATTHIAS MEIER, REPORT ON THE STUDENT THESIS:
'Plasmaprozess für InP-basierte Halbleiter mit niedrigen Ätzraten in einer Anlage mit induktivgekoppeltem Plasma' 28.04.2005 ALEXANDER VIESSMANN, REPORT ON THE DIPLOMA THESIS:
'Untersuchung eines vollständig integrierten und spannungsgesteuerten differentiellen Colpitts Oszillators für den WLAN Standard 802.11g' THOMAS GEISTERT, REPORT ON THE STUDENT THESIS:
'Optoelektronische Hochfrequenzcharakterisierung optischem Eingang'
von
MOBILE-Gattern
mit
02.06.2005 SERKAN TOPALOGLU, FRANZ-JOSEF TEGUDE, REPORT ON:
'17th Int. Conf. on InP and Related Materials' ( IPRM 2005), Glasgow, U.K., 08.05.2005-12.05.2005 A. MATISS, REPORT ON:
'German Microwave Conference' ( GeMic 2005), Ulm, FRG, 05.04.2005-07.04.2005 09.06.2005 S. TOPALOGLU, J. DRIESEN, REPORT ON
'Stand der Arbeiten im Rahmen des Projektes "InP-Elektronik für 80+ Gbit/s"' 16.06.2005 VICTOR KHORENKO, REPORT ON
'Stand der Arbeiten im Rahmen des Teilprojektes C3 des SFB 445 "Nanopartikel in Epitaktischen Heterostrukturschichten"'
Annual Report 2005 - Solid-State Electronics Department
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30.06.2005 A. MATISS, J. DRIESEN, REPORT ON:
'Stand der Arbeiten im Rahmen des Projektes "Super-ADC"' 07.07.2005 W. PROST, REPORT ON:
'Stand der Arbeiten zu RTD-HFET Schaltungen' WEI WANG, REPORT ON THE BACHELOR THESIS:
'SPICE Simulation optischer Empfängerverstärker mit PIN-RTD-HBT Bauelementen' 04.08.2005 KAI BAUMANN, REPORT ON THE STUDENT THESIS:
'Hochfrequenzcharakterisierung und Modellierung von Heterostruktur-Bipolartransistoren' 20.10.2005 JAN KALENDER, REPORT ON THE STUDENT THESIS:
'Entwicklung eines Programms zur Darstellung und Auswertung von HochfrequenzundGleichstrom-Messdaten an HBT' 03.11.2005 WERNER PROST, REPORT ON:
'6th Topical Workshop on Heterostructure Microelectronics' (TWHM), Hyogo, Japan, 22.08.2005 - 25.08.2005 10.11.2005 FRANZ-JOSEF TEGUDE, REPORT ON
'35th Europ. Solid State Device Research Conf.' (ESSDERC), Grenoble, France, 12.09.2005 - 16.09.2005 SERKAN TOPALOGLU, REPORT ON
'III/V - Workshop an Plasma Technologies', Zürich, Schweiz, 12.-13.09.05 24.11.2005 ANDREAS MATISS, REPORT ON
'Modellierung von Heterostruktur-FET: Modelle und Verfahren zur Parameterextraktion' 15.12.2005 JOHANNES HENZE, REPORT ON THE DIPLOMA THESIS:
'Automatische Charakterisierung von 3G-WCDMA Mobiltelefon-Leistungsendstufen zum Test digitaler Vor-Verzerrung'
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Annual Report 2005 - Solid-State Electronics Department
Annual Report 2005 - Solid-State Electronics Department
4 Research Activities
4.1 Materials, Growth and Characterization
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4.1.1
Annual Report 2005 - Solid-State Electronics Department
Growth, Processing and Characterisation of optimised GaAsSb DHBTs
Scientists: Technical Assistant:
S. Topaloglu, I. Regolin H. Barbknecht, A. Osinski
Introduction: Compared with the InGaAs/InP HBTs, GaAsSb-DHBTs offer lower offset and turn-on voltages, higher breakdown voltages, high current densities and better high frequency performance. This is mainly due to the staggered band line-up in this material system [1, 2, 3]. In the earlier phase of the GaAsSb-DHBT optimisation, some problems were experienced. From transmission line measurements, base contacts showed non-ohmic behaviour, which is attributed to the interlayer between base and emitter layers.
2
I (mA)
1 0 -8
-4
0
4
8
-1 -2 V (Volts) Fig. 1 I-V measurement of the base TLM contact structures for the former samples In addition to the metastable growth, the most important ones were; base emitter junction and the instability in the growth, which led to not reproducible GaAsSb DHBT layers. In this work, a method to achieve reproducible GaAsSb-DHBTs is investigated and tests have been performed to improve the base emitter junction quality. Test structures are grown to evaluate the growth quality. Experimental Set Up: The growth experiments are performed in a AIX200 RF low-pressure metal organic vapor phase epitaxy (LP-MOVPE) system with a fully non-gaseous source configuration. The DHBTs are processed using 3-mesa etching process. To identify the reasons for instabilities different structures have been grown and characterized. Sample A is the test structure having InP as collector and InGaAs as sub collector underneath the GaAsSb base layer, while the InGaAs layer is missing in sample B. X-Ray diffraction curves of both samples are given in figure 2. Although the p-GaAsSb layer had equal thickness and growth parameters, large difference in intensity and shape of the diffraction curve can be recognized. The metastable growth results in
Annual Report 2005 - Solid-State Electronics Department
15
shift in the peak as depicted in Figure 2. A layer thickness of 40 nm is calculated from the peak width of curve (b) in Figure 2. The signal (a) in Figure 2 indicates that there is a strong degradation in the crystal quality of the GaAsSb layer.
intensity log (a.u.)
InP (001) GaAsSb layer b) a)
-750
0
750
1500
2Θ [arcsec]
2250
Figure 2 x-ray diffraction curves of layers, including a p-GaAsSb layer. a) p-GaAsSb on a nInGaAs/InP collector (sample A) b) The structure without any InGaAs underneath the p-GaAsSb layer (sample B) We assume that the weaker binding strength of InAs in the InGaAs material, compared to that of InP [4], is responsible for the In carry over into the GaAsSb layer, which causes the HBT degradation in terms of crystal quality. When thicker InP collector layer is chosen, the HBT quality does not degrade. This also supports the idea about the carry over of In into GaAsSb. Additionally, for Sample B, an Sb poor content of around 40 % is calculated from the peak position of the diffraction curves. This lower concentration of antimony is intentional in order to reduce the already reported memory effect [1] and the segregation [5, 6] of antimony. As a consequence, the incorporation of antimony into the InP buffer layer is reduced. Considering the X-Ray results shown in Figure 2, we decided to replace the typical n++ InGaAs sub-collector layer with n++ InP. Two complete GaAsSb-DHBT layer structures are grown. The structure of both samples is as shown in table 1. The doping of base is 8x1019 cm-3 and 6x1019 cm-3 for Sample C and Sample D, respectively. Layer Emitter cap
Material n++ InGaAs
Emitter
n InP
Base
p++ GaAsSb
Collector
nid InP
sub collector n++ InP
Thicknes Doping s 1x1019 100 nm 1x1017 60 nm 19 C : 8x10 40 nm D : 6x1019 Nid 300 nm 1x1019
150 nm
s.i. InP Substrate
Table 1: Epitaxial layer structure parameters of fabricated GaAsSb DHBTs without the n-InGaAs sub collector
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Annual Report 2005 - Solid-State Electronics Department
Figure 3 presents the measured X-ray diffraction curves of two final DHBT layer stacks, including the associated simulation. The X-Ray results as well as the mirror like surfaces of both layers indicate perfect crystal quality and reproducibility. M 3 2 7C3 Sample
intensity log (a.u.)
s im u la te d m e a su re d
-7 5 0
M 3 3 5D 4 Sample
0
750
1500
2250
2 Θ [a rc se c ]
Figure 3 x-ray diffraction curves of samples A and B, including simulation results With these measurements, the stability of the complete growth process is proven. High material quality are also supported by current gain and ideality factors. For 1x15 µm2 device, a current gain of 35 is achieved. The ideality factors are identified as nBC =1.03 and nBE= 1.31 for the same device. Moreover, base contacts properties are also investigated. Here, ohmic behaviour has been observed for base TLM. The measured base sheet resistance is 1260 Ohm/sq and specific contact resistance is 7x10-6 ohm.cm2.
C E B Figure 4. The SEM picture of the processed Sb-DHBT (AE = 2x5µm2)
Annual Report 2005 - Solid-State Electronics Department
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RF measurements have also been done. In comparison to the former GaAsSb-DHBT samples with fT = 90 GHz and fmax = 50 GHz [7], these new samples show improved RF results: The HBT with an area of 1x15 µm² reaches fT = 115 GHz and fmax = 190 GHz at 1mA/µm2 current density. Conclusion: With this work, same problems faced in GaAsSb-DHBT growth are examined. The possible reasons for non-ohmic behaviour for the base contacts and the instability in GaAsSb-DHBT growth are investigated. By evaluation of different growth runs and sequences, it is concluded that the InGaAs sub collector is the problematic layer, which degrades the crystal quality. By replacing the InGaAs sub-collector with a highly doped InP sub-collector, the quality of the GaAsSb-DHBTs is improved and reproducible DHBTs are achieved. On the other hand, it is also shown that by using less Sb, the memory effect can be reduced. All of these features have been proven with x-ray measurements. GaAsSb-DHBTs are produced with this optimised epitaxial layer structures. They have shown a good performance of fT = 115 GHz and fmax = 190 GHz for a 1x15µm2 device. References [1]
C.R. Bolognesi, et al. “ Non-Blocking Collector InP/GaAs0.51Sb0.49/InP Double Heterojunction Bipolar Transistors with a Staggered Line-up Base-Collector Junction”, IEEE electron Device Letters, Vol. 20, No.4, April 1999
[2]
C.R. Bolognesi, et al. “ Investigation of High Current Effects in Staggered Line-up InP/GaAsSb/InP Heterostructure Bipolar Transistors : Temperature Characterization and Comparison to Conventional Type-II HBTs and DHBTs”, IEDM 2001
[3]
C.R. Bolognesi, et al. “ The Fabrication and Characterisation of High Performance InP DHBTs (invited)”, 12th GAAS Symposium – Amsterdam, 2004
[4]
C. Hilsum and A.C. Rose-Innes, “Semiconducting III-V Compounds”, Pergamon Press, page 25, 1961
[5]
C.X. Wang, O.J. Pitts, S.P. Watkins: “Time-resolved reflectance difference spectroscopy study of Sband As-terminated InP (100) surfaces”, J. of Crystal Growth, 248, (2003) 259-264
[6]
O.J. Pitts, S.P. Watkins, C.X. Wang, V. Fink, K.L. Kavanagh: ”Antimony segregation in GaAs-based multiple quantum well structures”, J. of Crystal Growth, 254 (2003), pp. 28-34
[7]
S. Neumann, et. al. “InP based double heterojunction bipolar transistors with carbon doped GaAsSb:C base grown by LP-MOVPE”, 11th Gallium Arsenide Application Symposium, Munich, Germany, October 6-7 2003
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Annual Report 2005 - Solid-State Electronics Department
4.1.2
Influence of Emitter Doping on the Performance of InGaAs/InPSingle Heterostructure Bipolar Transistors
Scientist:
J. Driesen
Introduction For the optimization of the performance of Single Heterostructure Bipolar Transistors (SHBT), most investigations concentrate on the reduction of parasistic resistances (bulk and contact resistances) and capacitances, mostly at the base-collector junction of the transistor. In this work, the influence of the emitter side on the DC and RF performance of the HBT is focussed. The influence of the doping is demonstrated by the comparison of two samples A and B with different emitter doping levels. The additional change of the sub-collector doping and thickness, which is both reduced to obtain a higher sheet resistance in the sub-collector layer for later circuit purposes (not discussed here), should not influence the transistor performance significantly. Table 1 lists the layer structures in comparison. Subsequent to the discussion of the DC performance of both transistors, the direct model parameter extractions from measured s-parameters will be presented to depict the changes for the junction capacitances and bulk resistances. Finally, the influence on the RF performance is discussed. DC performance influence The most apparent reason for this investigation is the current gain that is influenced by emitter doping NE as can be derived from [1] B=
I C DnB d E N E ∆WV = exp I B D pE d B N B kT
By increasing the doping, the amount of holes back-injected to the emitter is reduced, and therefore the gain is increased. This can be seen very well in the typical DC characteristics of the transistor, the Gummel plot and the output I(V) characteristics (fig.1).
Material
Doping
Doping
Sample A
Sample B
Emitter Cap
n-InGaAs
1,00e19
1,00e19
Emitter Contact
n-InP
1,50e19
1,50e19
Emitter
n-InP
2,00e17
1,00e18
Base
p-InGaAs
3,00e19
3,00e19
Collector
n-InGaAs
1,00e17
1,00e17
Sub-Collector
n-InGaAs
8,00e18
5,00e18
Table 1: Layer stack of both transistors.
Bulk Resistance [Ω] A B Emitter 3,95 2,54 Base 5,19 5,63 Collector 1,09 2,31
Inductance [pH] A B 12,6 16,5 53,8 56,9 54,9 53,4
Table 2: Resistance and inductance parameters.
Annual Report 2005 - Solid-State Electronics Department
1,E-01
11
1,E-02
9 Ic [mA]
1,E-03 1,E-04
Ib, Ic [A]
19
1,E-05 Ib - B
1,E-06
Ic - B
1,E-07
5 3 1
Ib - A
1,E-08
7
Ic - A
-1
1,E-09
0 0,4
0,5
0,6
a)
0,7
0,8
0,5
0,9
b)
Vbe [V]
1
1,5
2
Vce [V]
Fig. 1: Gummel-Plot (a) and output I(V) characteristics (b) of both samples in comparison. A second consequence of the doping can be seen from figure 1b. There is a drastical reduction of the offset voltage. Derived carefully [2], the offset voltage can be given as A N VCE ,offset ≅ VT ln C + VT ln C + Vbi , BE − Vbi , BC + ∆VCE − B − ∆VCB ,C AE NE By using this dependency, a theoretical VCE,offset = 0,13 V can be derived which fits very well the measured value.
Direct parameter extraction For determining the inner parameters of the transistor junctions and bulk resistances, detailed sparameter measurements in the range of 45 MHz up to 40 GHz have been utilized. All measurements were made on an Agilent 8510C vector network analyzer. For the derivation of the junction capacitances, these s-parameters have been measured with both junctions in reverse direction (VCE = 0 V, VBE < 0 V). In figure 2a, the C(V) characteristics of the transistor junctions of both samples are compared. The base-collector junction capacitances should not be affected by the emitter doping. The wet chemical etching for the base-collector mesa of sample B however has led to slightly more underetching, and therefore, CBC is less for sample B compared to sample A. 350
fT - B
Cbc
300
fmax - B
60
Cbe (M3364A)
50
Cbc(M3364A)
250
fmax - A
80
Cbe
f [GHz]
C [fF]
70
40 30
150 100
10
50 -2
a)
200
20 0 -1,5
-1
-0,5
Vbe [V] - Vce=0V
0
fT - A
0
0,5
0,5
b)
0,7
0,9
1,1
Jc [mA/µm²]
Fig. 2: Junction capacitances of both transistors in comparison (a), and resulting maximum frequencies (b).
1,3
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Annual Report 2005 - Solid-State Electronics Department
On the other hand, the base-emitter capacitance shows the expected more drastical increase for the higher doped emitter sample. Because of the higher emitter doping, the overall depletion region extent is reduced and shifted a bit more towards the base region. Since it can be seen as the dielectric of the junction capacitance, this increase of the capacitance is justified. To deduce the bulk resistances and parasitic inductances, the transistor has been measured in saturation region, so that the junction capacitances in parallel to them do not disturb the measurement of the differential resistance of the diodes. In table 2, the resulting (bulk) resistances and inductances are listed. The afore mentioned shift of the depletion region towards the base layer decreases the effective base width, which is an additional explanation for the increase of the current gain of the transistor. On the other hand, this causes an increase of the inner bulk base resistance, which can be seen in the resistance values listed in table 2 (since they are deduced from s-parameter measurements). The emitter resistance is decreased due to the higher emitter doping. Finally, the increase of the collector resistance is mainly originated by the initially mentioned change in the sub-collector layer of sample B (with the higher emitter doping). RF performance investigation So, as expected, by doping the emitter layer a bit higher, RE is decreased and the current gain is increased. These advantages are obtained with an increase of CBE and RB, and since these are important factors influencing the RF performance of the transistor, the maximum oscillation frequency fMAX and the transition frequency fT as figures of merit for the high frequency behavior have been addressed. In figure 2 b, the curves for both transistors are depicted in comparison. As it is apparent from the graph, the transition frequency has not changed remarkable, while the maximum oscillation frequency is a bit less for the higher doped sample. It can be seen in the diagram, that for the higher doped sample (B), the current density of the maximum frequency values is slightly increased. Concluding, the RF performance of the higher doped sample has not been reduced significantly. So, it seems that the positive and negative effects of the higher doping for the inner parameters are approximately compensating each other, while the advantages for the DC performance remain. Conclusion In this work, the effects of a higher emitter doping on the transistor DC and RF performance have been demonstrated, and theoretically explained. The main advantages are less offset voltage and an increased current gain. Although CBE and RB have increased, as was theoretically expected and experimentally proven by investigating the inner transistor junction parameters and bulk resistances, only a slight reduction of fMAX and no significant change of fT have been observed. So, this work results in transistors which are able to give better support for digital as well as analog applications. References: [1] [2]
W. Liu; "Fundamentals of III-V Devices“, Wiley-Interscience publication, John Wiley & Sons, ISBN 0-471-29700-3. J. J. Liou; "A study of the collector-emitter offset voltage of InAlAs/InGaAs and AlGaAs/GaAs heterojunction bipolar transistors“, Semiconductor Science Technology 5 (1990), pp. 355-357.
Annual Report 2005 - Solid-State Electronics Department
4.1.3
21
On the impact of the Carrier Gas on the MOVPE Growth of In0.53Ga0.47As/InP HBT
Scientist: in collaboration with Technical Assistant:
I. Regolin, S. Topaloglu, S. Neumann, W. Prost Dr. Satoshi Taniguchi, Sony Corporation, Atsughi-shi, Japan R. Geitmann
Introduction InP HBTs are of pronounced interest for high-speed circuits requiring a very high power-added efficiency. The MOVPE equipped with all-liquid sources [1] is a promising technique for highvolume production of InP-based HBT. Among others the choice of the carrier gas, nitrogen (N2) or hydrogen (H2), is an important factor in terms source efficiency and doping capabilities. Using the N2 carrier gas the surface temperature at the growth interface is substantially lower enabling a higher carbon take-up in the epitaxial layer. Hence, the use of N2 carrier gas has revealed an ease of receiving a very high hole concentration in the InGaAs:C base layer [2]. However, the lower surface temperature and the different temperature profile in the reactor completely changes the growth conditions and may have a strong impact on the source efficiency. In this study, a comparison of the impact of the carrier gas on the growth conditions in an Aixtron LP-MOVPE with RF heating is given for the growth of InP-based HBT layer. As source materials TEGa, TMIn, TBAs, TBP, DitBuSi, and CBr4 are used. During cool-down, TMAs was used for surface stabilisation. The growth temperature Tg always represents the thermocouple temperature. N-Type Doping
10 InGaAs:Si + N2 H2 Tg = 620 °C
8
carrier concentration nH / cm-3
carrier concentration nH / 1019 cm-3
InGaAs.Si lattice matched to InP has been grown at Tg = 620 °C. The samples were investigated by room-temperature Hall measurements. The Silicon doping is adjusted with DitBuSi/group-III flow ratio. N++-InGaAs is investigated here, because high doping levels in the 1019cm-3 range are needed in the HBT for the emitter-cap and the sub-collector.
trend H2
6 4 2 0
trend N2 ++ 0
a
Figure 1.
20
+
+
60 40 QDitBuSi .103 QDitBuSi + QTMIn + QTEGa
+ ++ +++ + 80
19
10
18
10
InP:Si + N2 H2 Tg = 600 °C
17
10
trend H2
+
+
+
+
trend N2
+ ++ +
+
16
10
15
100
10
b
0.001
0.01
0.1 1 QDitBuSi .103 QDitBuSi + QTMIn + QTEGa
Silicon n-type doping efficiency using DitBuSi for (a) InGaAs and (b) InP.
10
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The doping efficiency for H2 and N2 carrier are compared in Fig. 1a. Under H2 carrier the doping efficiency is three times higher. Moreover, the n++-InGaAs:Si layer exhibit a higher mobility. I. e. the sample doped to 3.4.1019cm-3 exhibits a mobility of 1200 cm²/Vs while the counterpart under nitrogen carrier exhibits a 30 % lower mobility. InP is used in the HBT in a wide doping range because InP:Si may be used as collector, doped collector, emitter, and emitter cap resulting in doping requirements from 0….1019cm-3. Fig. 1a represents InP:Si grown at Tg = 620°C in a wide doping range. The doping efficiency under H2 carrier is about 3..10 times higher compared to nitrogen. In addition, the growth rate under H2 carrier is 70 % higher representing the better source take-up. The mobility data are for the same doping level also comparable or surprisingly somewhat worse using H2 carrier. InGaAs:C The base layer of high-speed HBT requires a hole concentration in the 1019cm-3 range. A high ptype concentration is achieved at low growth temperature and low V/III ratio, only. Under H2 carrier gas the incorporation of carbon into the host lattice is lower compared to nitrogen carrier gas. Consequently, the growth temperature using H2 carrier has to be reduced to 480 °C in comparison to 500 °C in case of N2 gas.
SONY EMCS material analysis center
P->
10 20
As->
Cs+
C 10
19
10
18
10
InP
10
H 2 carrier
H
10
8
7
6
Br 10
5
M3224
10
17
0
a
Figure 2:
100
200
300
depth / nm
400
10 500
4
10 20
n-InGaAs InP InGaAs:C
InGaAs n.i.d. 10
As
P
6
C
10 19
10
5
N 2 carrier
H
10 18
10
4
M 1881
10
17
H 10 O
10
b
O
16
100
200
300
3
400
10 500
2
Secondary Ion Intensity / Count / sec.
InGaAs:C
concentration [atoms/cm3]
concentration [atoms/cm3]
10 21
Secondary Ion Intensity / Count / sec.
Fig. 2 shows the SIMS spectra of samples incorporating InGaAs:C grown with different carrier gas. The single InGaAs:C layer sample was grown with H2 carrier gas (Fig. 2a). The carbon atom concentration is nC = 4.10-19cm-3 while the Hall measurement gives a net hole concentration of p = 2.10-19cm-3. This results in an activation ratio of p/nC = 0.5 while the hydrogen incorporation in the lattice is nC/nH = 4. In comparison the SIMS spectrum of a SHBT grown under N2 carrier is given Under N2 carrier we have obtained for an nC = 1.2.10-19cm-3 an activation ratio of p/nC = 0.8 [1] while the hydrogen incorporation in the lattice is again nC/nH = 4 (cf. Fig. 2b). These results indicate that the carrier gas has a negligible impact on the carbon activation.
depth / nm
Secondary Ion Mass Spectroscopy of InGaAs:C (a) single InGaAs:C layer grown with H2 carrier and (b) InGaAs/InP SHBT with InGaAs:C base layer grown with N2 carrier.
The results in fig. 2 indicate that the carrier gas has a negligible impact on the carbon activation. On the other hand hydrogen radicals (H, H+) are responsible for the deactivation of carbon on Aslattice sites. In MOVPE growth both standard As-precursors TBAs (AsH2(C4H9)) or arsine (AsH3)
Annual Report 2005 - Solid-State Electronics Department
23
are producing hydrogen radicals. Hydrogen radicals are all-important for the decomposition of the the metal organic precursors and for the take-off of not used components (forming CH3 to CH4) from the surface during growth especially at the low growth temperatures used for InGaAs:C. Moreover, during doping with CBr4 (or CCl4) the halogenics also reduce the free amount of hydrogen radicals. P-type doping of InGaAs:C requires a carefully balance of hydrogen radicals at the growth front. Therefore, hydrogen radicals may only be avoided at the time when they are no longer in use: during cool-down. Here, TMAs (As(CH3)3) is used for surface stabilisation because its decomposition does not result in the production of hydrogen radicals. On the other hand, the growth rate of low-temperature grown InGaAs using TMAs is negligible due to the lack of hydrogen radicals. Conclusions High quality InP-based HBT layer sequences may be grown either with H2 or N2 carrier gas. Due to the higher surface temperature and the different temperature profile the source take-up under hydrogen is substantially better, i. e. the growth rate for InP is 70 % higher using H2 carrier gas. This is an important factor for production. On the other hand, a high net hole concentration in InGaAs:C requires an about 20 °C lower thermocouple temperature under H2 compared to N2. For future works a HBT layer stack growth with N carrier for the base, only, may be a technically and economically interesting solution. Acknowledgement Thanks to Akzo Nobel (Dr. J. Koch, Dr. E. Majoor) for the support of this work and intense discussion on MOVPE precursor. References: [1] P. Velling, Zur metallischen Gasphasenepitaxie (MOVPE) mittels nicht-gasförmiger Quellen für elektronische Heterostruktur-Bauelemente basierend auf III/V Halbleitern, ISBN: 3 - 932392 - 35 – 3. [2] D.Keiper, P.Velling, W.Prost, M.Agethen, F.J.Tegude, G.Landgren; Metalorganic Vapour Phase Epitaxy (MOVPE) Growth of InP-based Heterojunction Bipolar transistors (HBT) with Carbon Doped InGaAs Base Using tertiarybutylarsine (TBA), tertiarybutylphosphine (TBP) in N2 Ambient, Jpn.J.Appl. Phys. vol. 39, pp. 6162-6165, 2000.
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4.1.4
Annual Report 2005 - Solid-State Electronics Department
Application of atomic hydrogen source in the molecular-beam epitaxy
Scientist: Technical Assistant:
V. Khorenko R. Geitmann
Introduction Ae highest degree of material purity is a prerequisite for robust and high performance electronic devices and circuits. The first critical step in the whole device fabrication cycle is the removing of oxides from the wafer surface prior to the epitaxial growth. Even a small amount of oxide residuals and contaminations may significantly deteriorate the quality of grown heterstructures. Besides the conventional procedure with annealing of GaAs of InP wafer at corresponding As2 or P2 counter pressure, the irradiation by atomic hydrogen H+ is often used [1]. Because of a high reduction potential, the employment of free hydrogen radicals H+ allows to reduce annealing temperatures in comparison to the conventional one`s and to keep the material stoichiometry. Moreover, H+ is also known as a good diffusion promouter that increases the sufrace mobility of adatoms and, therefore, improves the flatness of the grown layers and their interfaces [2]. Usually, hydrogen sources will be mounted in a separate chamber and not in the growth chamber. This restricts the application area to the low-temperatutre wafer cleaning only, but allows to avoid a possible contamination of the source by semiconductor material components, mostly arsenic. In this contribution, preliminary results of application of an atomic hygrogen source in the molecular beam epitaxy will be described. Among the influence of hygrogen on the oxide desorption and the grown layers quality, the source contamination due to continious arsenic backgroung pressure during the epitaxy was estimated. Technical details We mounted an atomic hydrogen source (Tectra GmbH) in the growth chamber of a MBE-machine Varian GEN II on a standard cell port. For the hydrogen supply, the common hydrogen gas line (5N purity grade) in the clean room was extended to the source input port. A nitrogen gas line was also connected through a mass flow-controller to the hydrogen line for the line purge prior to growth experiments. The working principle of this source is based on the thermal cracking of molecular hydrogen passing through a capillar tube heated up to 1900 °C. Due to a very small diameter of the tube (few micrometers), the cracking efficiency reaches about 90% (according to the product specifications). The cracking temperature is adjusted by an external high voltage source. Since the measurement of atomic hygrogen pressure with a standard vacuum gauge is very inaccurate, the gas flow was adjusted with molecular hydrogen at a BEP of 5.10-7 Torr prior to switch on the voltage source.
Annual Report 2005 - Solid-State Electronics Department
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Experimental results For the experiments on the oxide cleaning using the hydrogen source, InP and GaAs undoped (100) substrates were used. Since the hydrogen source was mounted in the growth chamber, the oxide removal was done in the presence of As2 flux. The surface oxide removal was observed with RHEED and also confirmed by results of electrical characterisation of the grown and processed HEMT structures. It was found that in case of InP substrate, the cleaning temperature in presence of atomic hydrogen may be reduced by more than 100°C (from 630°C to 530 °C) without degradation of electrical performance of fabricated HEMTs. Reducing effect of atomic hydrogen was also observed in experiments with the cleaning of metallic In nanoparticles synthesised in the gas-phase and deposited of a GaAs substrate. It is planned to employ these In particles for the fabrication of novel nanostructures by embedding them into a GaAs matrix. During the last year an aerosol generator was integrated in the MBE machine, that allowed to avoid the sample transfer through air and, therefore, strong oxidation. Annealing procedure with atomic hydrogen is the final step towards the contamination removing from the nanoparticle surface.
Si3N4 As Si
In-situ melting of a single In particle
time Fig.1 STEM images of the melting of a single In nanoparticle (~30 nm diameter) embedded in an amorphous arsenic layer during heating by electron beam of the electron microscope. Figure 1 shows a series of cross-section images of a single In nanoparticle in an arsenic layer done by scanning transmission electron microscope. At a low magnification (i.e low electron beam energy), the particle is stable and does not change its form with the time. A higher electron beam energy leads to the particle melting, since the melting point of indium is ~150 °C. In the investigated structure, the melting process is also accompanied by the desorption of the surrounding arsenic layer and appeares as light areas in the image.
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Annual Report 2005 - Solid-State Electronics Department
The possibility of contamination of this source by metallic arsenic was estimated in order to estimate the failure risk due to the short-circiut of high voltage connectors of heating filament. This study is especially important, since, in comparison to other material cells, the hydrogen source stays mostly cold that can lead to the enhanced condensation of growth species. In our experiments, permanent arsenic overpressure inside the growth chamber resulted in this failure after four months of operation only. Optical inspection of all inner parts showed a thin conductive coating on ceramic insulators that provides a parasitic electrical conductivity. After an exchange of the contaminated part, a temporary protection of the critical area was done by a teflon plate. A modification of the source with respect to the better stability against arsenic condensation is planned by the manufacturer. Conclusion Atomic hydrogen installed in the in the growth chamber of an Varian GEN II MBE machine is effectively used for oxide removing from InP and GaAs wafer and cleaning of the surface of metallic In nanoparticles. An As condensation on inner parts of the source may lead to the electrical failure and requires a further hardware modification. References: [1] [2]
T. Sugaya, M. Kabawe, “Low- temperature cleaning of GaAs surface by atomic hydrogen irradiation”, Jp. J. of Appl. Phys. , v.30 , p.L402 , 1991. Y. J. Chun, Y. Okada, M. Kabawe, “Enchanced two-dimansional growth of GaAs on InP by molecular beam epitaxy with atomic hydrogen irradiation“, Jp. J. of Appl. Phys. , v.32 , p.L1085 , 1993.
Annual Report 2005 - Solid-State Electronics Department
4.2 Device and Circuit Processing
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4.2.1
Annual Report 2005 - Solid-State Electronics Department
Influence of Collector Doping on HBT Performance
Scientists: Technical Assistant:
S. Topaloglu H. Barbknecht
Introduction: The figures of merit for high frequency performance are the cut-off frequency fT and the maximum frequency of oscillation fmax [1]. kT kT 1 = τbase +τ collector + Cje + Cbc + Rex + Rcoll qIE 2π ⋅ fT qIC
(1)
fT 8π ⋅ RBB C BC
(2)
f max ≅
As it is depicted in equation (1), the cut-off frequency is limited by the transition times, which are mostly influenced by the vertical dimension of the HBT structure. The maximum oscillation frequency is additionally affected by the parasitic capacitances and resistances, which can be controlled by lateral scaling of the devices. Briefly, fT can be improved by epitaxy and processing and while the layout mainly improves fmax. By decreasing the base and collector thickness, the transit frequency fT can be improved but at the same time fmax may be affected adversely. In this work, we have investigated the effect of collector doping on the improvement of fT. At a high collector current density ( J C > q N dC v sat ), the electron density entering the base collector depletion region exceeds the doping level and this changes the electric field profile at the junction. This will cause na increase of hole injection from base to collector and so incerasing base width. The extended base width results in increased base transit time and aslo degraded current gain. This high current density effect is the well-known Kirk Effect [2,3]. Doping of the collector (NC) may oush the Kirk current density to higher levels. Experiment: The structures are grown by LP-MOVPE (Low Pressure-Metal Organic Vapour Phase Epitaxy) (Aixtron 200) on (001) ± 0.5° oriented semi insulating (001) InP (Fe) substrate. Three samples were used for this investigation. Sample A, Sample B, and Sample C have the same layer structure as depicted in table 1, but the collector doping differs. The collector doping is nid (A) (nonintentionally doped), 5x1016cm-3 (B), 5x1017cm-3 (C), respectively. These samples are processed in parallel, to eliminate any deviation that may occur by environmental effect during processing. Device fabrication is carried out by conventional wet chemical etching based on phosphoric acid (H3PO4) for InGaAs and InGaAsP layers, and hydrochloric acid for InP containing layers. The emitter, base and collector layers are defined by optical lithography. The Ti/Pt/Au contact metal system is used for emitter and collector contacts. The self-aligned base metallization is deposited as
Annual Report 2005 - Solid-State Electronics Department
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Pt/Ti/Pt/Au. Air bridges are used for the connections to the measurement pads. SEM (Scanning Electron microscope) micrograph of one of the realized HBTs is shown in Figure 1. 2µm
B
C E
Figure 1. SEM picture of HBT with nominal AE= 2x10 µm2
Results The DC characteristics of the DHBTs were measured by an HP4515B parameter analyzer. 18 16 14
Sample A Sample B Sample C
IC (mA)
12 10
∆ IB=50µA
8 6 4 2 0 0,0
0,5
1,0
1,5
2,0
2,5
3,0
3,5
4,0
4,5
5,0
5,5
6,0
V CE (V)
Figure 2. Common Emitter Output Characteristics for Sample A, B and C In figure 2 common emitter output characteristic for sample A, B and C are shown. The DC current gain is ~70 for all three samples at IB=200µA. The breakdown voltage has decreased by increasing collector doping. (BVCEsampleA= 5.5V, BVCEsampleB = 4.5V, BVCEsampleC = 3V) High frequency measurements using an HP8510C network analyser, have been performed. For these measurements on devices with AE=2x10µm2. Sample A, B and C have shown transit frequency (fT) of 100GHz, 120GHz and 165GHz, respectively.
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Annual Report 2005 - Solid-State Electronics Department
Th ecalculatiom of Kirk current denisty is given in equation 3.
J Kirk = (1 +
VCB + φCB ) q N C vsat V2 + φCB
(3)
where:
φCB
: Base collector junction potential
V2
: applied base-collector bias that totally depletes collector layer when JC=0
NC
: Collector doping
vsat
: Saturation velocity
Calculated Kirk current densities (JKirk) are as follows; JKirk,A=0.9mA/µm2, JKirk,B=2.5mA/µm2, JKirk,C=6.5mA/µm2. These values fit really nice with the values measured.
180 160 Sam ple C; fT
140
Sam ple B; fT Sam ple A; fT
fT (GHz)
120 100 80 60 40 20 0 0,001
0,01
0,1
1 2
J C (mA/µm )
Figure 3. fT vs. Current density
10
Annual Report 2005 - Solid-State Electronics Department
31
7
10 8 6
4 3
4
2
BVCEo (V)
5
2
JKirk (mA/µm )
6
2
1 0
1x10
17
2x10
17
17
3x10
4x10
17
5x10
17
0 17 6x10
-3
NC (cm )
Figure 4. Compromise for collector doping to JKirk and breakdown voltage The effect of collector doping on the JKirk and collector emitter breakdown voltage can be seen at the same time. The measured Kirk current densities show good agreemment with the calculated values. Conclusion
The Kirk effect has been experimentally observed in DHBTs with varied collector doping densities. It has been found out that doping the collector can reduce this effect. This will lead to better RF performance. On the other hand, the collector doping decreases the breakdown voltage. The experimental results are compared with the theoretical calculations and good agreement has been achieved.
References [1] [2] [3]
Rodwell, M.J.W.; et. al, Submicron scaling of HBTs Electron Devices, IEEE Transactions on, Volume 48, Issue 11, Nov. 2001 Page(s):2606 - 2624 C.T. Kirk, A theory of Transistor Cutoff Frequency Fallof at High Current Densities, IRE Transactions on Electron Devices, March 1962, page: 164-174 William Liu, Fundamentals of III-V Devices; HBTs, MESFETs, and HFETs/HEMTs, John Wiley &Sons, Inc., page186-196
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Annual Report 2005 - Solid-State Electronics Department
4.2.2
Plasma process for InP-based semiconductors with low etch rates using an ICP-System
Student: Supervisor:
M. Meier S. Topaloglu
Introduction In the manufacturing of HBTs (heterobipolartransistors), the etching process may play a very important role. For the realization of submicron structures, wet chemical etching does not offer sufficient solutions, since it is isotropic. For these kind of structures, dry etching techniques can be preferred. Another advantages of dry etching are the reliability and reproducibility of the processes, so that etch rates and sidewall profiles can be controlled easier than using wet chemical etching. The aim of this work is to elaborate processing with low etch rate using ICP-RIE system (Inductively Coupled Plasma–Reactive Ion Etching) with Cl2/N2 chemistry. Since it does not contain H2, this chemistry prevents hydrogen passivation.
The ICP-RIE System used Figure 1 shows the system (Oxford Instruments PlasmaLab System 100 ICP65) which is installed in our clean room. With ICP-RIE, it is possible to control the ion density and ion energy independently, by the help of two independent RF sources. The ICP-source creates the plasma whereas the RF-source, which is connected to the sample-chuck (lower electrode), supports the acceleration of the ions towards the sample. Consequently the etch process can be controlled better in comparison to an parallel plate system.
Loadlock
ICP-source
Processchamber
Temperature of the chuck Controller of the turbopump Figure 1. Oxford Instruments Plasmalab100 ICP65
Annual Report 2005 - Solid-State Electronics Department
33
The process chamber, on which the ICP-source is installed, encloses the sample chuck. The chuck also represents the lower electrode of the system, so that ions can be forced into the direction of the sample. On the other hand the chuck can be cooled (to – 150°C) or heated (to + 400 °C). The heating of more than 150°C is necessary to remove the involatile InClx from the surface of the etched sample. From the backside of the sample, helium flow is applied to provide thermal contact with the chuck. The system contains three gas lines for the process gases chlorine, nitrogen and oxygen. Cl2 and N2 are used for the etching process, whereas O2 is used to clean the chamber after etching. In the case of ICP-RIE etching with chlorine and nitrogen the mechanism of etching is called ion enhanced chemical etching. Cl2 is responsible for the chemical reaction with the semiconductor and N2 enhances the removal of the reaction products, here InClx and PClx. So nitrogen builds a mechanical component of the etch mechanism. The gas mixture or the gas ratio Cl2/N2 is very important for the process. According to which component dominates etch mechanism, the roughness of the surface and the characteristic of the sidewalls will change. With this technique it is possible to achieve vertical etch profiles as shown in figure 2. For our application (HBTs) it is not possible to use hydrogen based chemistries (e.g. CH4) Since base is carbon doped, Hydrogen can passivate the dopants, which is named as hydrogen passivation. With the load lock, the chamber stays cleaner (e.g. by humidity in the air), because for an etching process only the load lock needs to be opened. The vacuum of the load lock and the chamber is pumped with a combination of a turbopump and a prepump from Leybold. The system is controlled via an external PC. Using the software PC2000, the operator can define several parameters like temperature, pressure or gas mixture for each etching process. It is also possible to create recipes, which are used for an automatic etching process.
Cl+
N+
Volatile product
Figure 2. Etching mechanism using Cl2/N2-chemistry Etching results To find a process which is suitable for HBT applications it was necessary to analyse the influence of several parameters on the etching. Therefore we made four test series to see the effect of temperature, pressure, gas ratio and RF-power on the etch rate and on the surface roughness. During each series of experiments all parameters except the one that was tested were held constant. For the fabrication of test structures approximately 500 nm lattice matched InGaAs was grown on InP. The samples were structured with metal stripes of different orientation and width (see figure
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Annual Report 2005 - Solid-State Electronics Department
3). Here it is not that important whether InP or InGaAs is etched, because each material includes the critical indium component, so that there is not a great difference in their behaviour during the etching process.
Figure 3. Structured InP/InGaAs-sample The small wafer pieces has to be glued on an 2” Si-wafer, because the system is prepared only for 2” wafers.
r [µm/min]
Etch R ate vs Temperature 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0
50
100
150
200
T [°C]
Figure 4. Etch rate vs. temperature It can be seen that the etch rate changes for all parameters. If the temperature becomes higher than 150°C the InClx gets volatile, so that the material can be removed from the surface easier at high temperatures. Also, by applying more RF-Power to the lower electrode of the system the etch rate goes up, because ions get more accelerated to the surface.
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Etch Rate vs RF Power 0,8
r [µm/min]
0,7 0,6 0,5 0,4 0
50
100
150
200
PRF [Watt]
Figure 5. Etch rate vs.RF Power The RMS-roughness of the surface stays less than 6 nm, which is comparable with the literature. The pictures of SEM (scanning electron microscope) show a very good achievement in terms of vertical sidewalls. In the very last experiment an etch rate of 185 nm/min could be achieved by using a low RF-power (50 Watt) and a low temperature.
Figure 6. SEM micrograph of an etched sample, vertical sidewalls are achieved
Conclusion In this series of experiments we were able to find the suitable parameters for the following HBT process. For this, a low etch rate and a vertical sidewall were realized. The parameters which have been discussed can now be used in a controllable way. Now it is possible to produce sub-micron emitters, so that the base resistance and the base-collector capacitance of HBTs can be minimized for the future.
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4.2.3
Annual Report 2005 - Solid-State Electronics Department
Development of pinip-Photodetectors with High Functionality for Digital Circuits
Scientist: Technical Assistant:
A. Poloczek H. Barbknecht
Introduction Photo detectors are the key components between optical data transmission and electronic data processing. Their monolithic integration enables the development of opto-electronic integrated circuits (OEIC). III/V compound semiconductors exhibit a direct band gap for high quantum efficiency at the wavelength of the optical fiber communication at λ = 1.3 µm and 1.55 µm. To reduce the chip area and the complexity of OEICs, the increase of functionality of photo detectors is desirable. One approach is to stack multiple absorption layers with different band gaps [1].
contact layer absorption layer
AR-coating p-InGaAs (50 nm) i-InGaAsP (600 nm)
λ=1.3µm
metallization contact
i-InGaAs (600 nm)
λ=1.55µm
n-InP (100 nm)
p-InGaAs (200 nm) InP-buffer (40 nm) InP-substrate
Figure 1.
Cross section of a pinip-layerstack after processing
Here different signals, modulated with different wavelengths, can be injected into the detector in parallel. The detection takes place in different absorption layers due to the transparency of the upper layer to the higher wavelength. Thus, the oe-conversion and the optical demultiplexing of data is done simultaneously.
Annual Report 2005 - Solid-State Electronics Department
37
Technology •
Epitaxy
The investigated semiconductor layers were grown by MOVPE with a non-gaseous source configuration lattice matched on InP. The band gap of the quaternary absorption layer is adjusted to approximately 0.9 eV. The lower absorption layer is realized by nid-InGaAs. Both pin-diodes share the n-InP contact layer. This means, they have a common cathode contact. This simplifies the layer stack and process, but it reduces the degree of freedom during the circuit design with this device. As standard dopant for highly doped p-InGaAs contact layers we use carbon. In comparison to the p-InGaAs:C top layer, we observed a degradation of doping density in the buried p-InGaAs:C layer of approximately one order. This leads to an unacceptable high contact resistance for the lower pindiode. Thus, we decided to investigate zinc as p-dopand for the buried contact layer and we observed a much more stable dopant density [2]. The possible cause for this effect is an insufficient activation of carbon doping or a degradation of the buried layer by the growth temperature of the upcoming layers. The layer configuration with burrowed p-InGaAs:Zn was suitable for first working pinip-devices. •
Process technology
The devices were processed by optical contact lithography and conventional wet chemical etching using a triple mesa design with ring metallisation on each contact layer. The critical etching of 600 nm nid-InGaAsP was performed by H2SO4:H2O2:H2O (1:1:10) with an etch rate of ~ 2 nm/s highly selective on InP. The underetching slope and mesa surface is acceptable but it will be optimized with a dry etching process in future. To manage the contact bridges between the measurement pads and the intrinsic device with a total height up to 1.6 µm, a spin on glass (BCB) is used to support the strip line.
Figure 2.
Layout (left) and micrograph picture of a fabricated pinip-single device (right) with 21 µm diameter active area
Measurement Results The processed pinip-devices are characterized concerning their DC I/V-characteristics and responsivity (see fig. 3). The dark current of the InGaAs-diode moves in a typical range of ~20 nA.
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Annual Report 2005 - Solid-State Electronics Department
Looking at the upper InGaAsP-diode the dark current reaches values, which are approximately one order higher. This might be caused by the crystal quality of the quaternary material and the mesa surface of the upper absorption layer.
Figure 3.
DC-Measurements and responsivity results of the upper and the lower pin-diode
The responsivity measurements were accomplished with a cw-semiconductor laser providing λ=1.3 µm and λ=1.55 µm. The optical input propagates through a cleaved fiber, which is adjusted over the device. With regard to the InGaAsP-diode, the generated photocurrents differ at approximately two orders. This selectivity is not reached by the lower InGaAs-diode by far. The measured resposivities are close to each other. Thus, the resulting crosstalks are C1,55µm = - 20.6 dB and C1,3µm = - 0.19 dB. The optimization of crosstalk on λ=1.3 µm is in progress. The work on pinip-devices continues with investigation of the RF-performance. Conclusion Within the last period, epitaxy and process was investigated for high functionality demultiplexing photodetectors. First measurement results certify a high potential to translate the idea of stacked absorbing layers into a device suitable for digital circuits with high bit rates. Further investigation is necessary to overcome some difficulties mentioned above. References: [1] [2]
J.C.Campbell, A.G.Dental, T.P.Lee, C.A.Burrus; "Improved Two-Wavelength Demultiplexing InGaAs Photodetector", IEEE J. of Quantum ELectronics, Vol. QE-16, No.6, June 1980 A. Poloczek, I. Regolin, F.-J. Tegude, W. Prost; „Wachstum und Anwendung von InGaAsP-Schichten für optoelektronische Detektoren mit gestapelten Absorptionsschichten“, 20. DGKK Workshop "Epitaxie von III/V-Halbleitern", 8./9. Dezember 2005, Duisburg
Annual Report 2005 - Solid-State Electronics Department
4.2.4
39
Realization of High Performance InGaAs pin-diode on Silicon Substrate
Scientist:
A. Poloczek
Introduction The co-integration of optoelectronic III/V-devices with CMOS technology on silicon substrate is one promising approach to combine the advantages of both technologies. With regard to compound semiconductor optoelectronic devices, such as light emitters or photodetectors, a successful fusion with silicon data processing provides the opportunity for mass produced ultra broadband opto elctronic integrated circuits (OEIC) for optical communication. Our efforts on this topic provided device model fundamentals for simulation of co-integrated OEICs [1,2]. With the presented successful RF-measurement on a III/V pin-photodetector grown on silicon, the investigation has got a step forward. Technology Because of the lattice mismatch between silicon and InP, the growth of an InP quasi-substrate is necessary, prior to the epitaxy of the device layers. After a wet chemical and high temperature treatment to remove the native silicon oxide, the quasi-substrate was grown in a low-pressure MOVPE at 400°C [3]. In order to reduce the surface roughness (RMS) from 3.4 nm to 1.9 nm and completely zero out small defects, the 1.5 µm thick quasi substrate is overgrown with 200 nm lowtemperature InAlAs in MBE, lattice matched on InP [4]. This surface is suitable for growth of III/V active layers. isolator (BCB) III/V pin-epilayers
an
od
ca th o
e
de
metal contact
LT - InAlAs InP buffer
200 nm 1.5 µm
Si substrate (001)
Figure 1.
Qualitative configuration of processed device on silicon substrate (left) and a optical micrograph of the InGaAs pin-diode (right)
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Annual Report 2005 - Solid-State Electronics Department
On the treated Si-substrate, the pin-diode was grown by LT-MOVPE with non gaseous precursor configuration. The layer stack consists of a 650 nm nid-InGaAs absorption layer (TEpi = 680°C), positioned between highly doped p-InGaAs:C and n-InGaAs:Si contact layers. The devices were processed with optical contact lithography and wet chemical etching in a double mesa design. To avoid parasitic quasi-substrate leakage current, the substrate was covered with a high isolating spin on glass (BCB, ρBCB = 1E19 Ωcm) prior to processing of contact pads. Measurement results The investigated pin-devices have an active area diameter of 21 µm. The determined responsivity of the pin-diode on silicon with 650 nm absorption length reached values of 0.55 A/W at Ubias = -1 V and is absolutely comparable with values of devices on InP substrate. In comparison to InGaAs pindiodes on InP substrate, the I/V-characteristics on silicon show clearly a higher dark current. This phenomena can be traced back to the trap supported diffusion of silicon from substrate into the nidInGaAs layer during epitaxy. These traps promote the recombination of thermally generated electron-hole pairs.
Figure 2.
Dark current comparison of pin-diodes on InP / Silicon and responsivity result on silicon
Furthermore, the RF-performance of pin-diodes on silicon was investigated by measurements in the frequency domain. Therefore, the device was biased in reverse direction at Ubias= -1 V. A 1550 nm cw-laser beam was modulated with a 10 GHz electrical sinus signal by an electro absorption modulator (EA). The resulting 10 GHz optical signal was guided through a cleaved fiber into the device. The frequency response of the pin-diode was catched by a 50 GHz digital oscilloscope. The result can be seen in figure 3. The measured eye pattern shows an open eye at 10 Gbit/s and approves the functionality of the device at high frequencies. Therefore, the used optical input power of -3 dBm is far below the maximum operation limits of the diode.
Annual Report 2005 - Solid-State Electronics Department
Figure 3.
41
10 Gbit/s eye pattern of 21 µm pin-device on silicon at Ubias= -1 V and Popt= -3 dBm
Conclusion High quality III/V pin-epilayers were successfully grown on silicon substrate by the help of a quasisubstrate. The properties of the epilayers were demonstrated by processing and measuring of resulting pin-diodes. The measurement data certifies resposivity comparable to state-of-the-art InP pin-diodes and excellent operation up to 10 Gbit/s. Acknowledgement Optical RF-measurements were provided by the department of optoelectronics at University Duiburg-Essen. The supply with silicon samples with InP quasi-substrate as starting material for our research group by the TU Braunschweig, Institute of Semiconductor Technology, Prof. A. Schlachetzki is greatly acknowledged. References: [1] [2] [3] [4]
W. Prost, et al.; “High Performance III/V RTD and PIN Diode on a Silicon Substrate”, 6th Topical Workshop on Heterostructure Microelectronics, TWHM Awaji Island, Hyogo, Japan 2005 W. Prost, et al., “Design and Modeling og a III/V MOBILE-Gate With Optical Input on a Silicon Substrate”; 17th Indium Phosphide and Related Materials Conference, Glasgow, UK 2005 A. Bakin, D. Piester, I. Behrens, H.H. Wehmann, E. Peiner, A. Ivanov, D. Fehly, A. Schlachetzki; Journal of Crystal Growth & Design, American Chemical Society, Vol. 3, Nr. 1, 2003, pp. 89-93 V. Khorenko, A. C. Mofor, A. Bakin, S. Neumann, A. Guttzeit, H.H. Wehmann, W. Prost, A. Schlachetzky, F.-J. Tegude; „Buffer Optimization for InP-on-Si (001) Quasi-Substrates“, 16th InP and Related Materials Conference, Kagoshima City, Japan 2004
Annual Report 2005 - Solid-State Electronics Department
4.3 Device and Circuit Simulation, Measurement and Modeling
43
44
4.3.1
Annual Report 2005 - Solid-State Electronics Department
Low Temperatur Characterisation of SiGe Resonant Tunneling Diodes
Scientist:
A. Matiss
Cooperation with:
Douglas Paul, Sam Suet , Semiconductors Physics Group, University of Cambride, England
Introduction: Resonant Tunneling Diodes exhibit a negative differential resistance in their I/V-characteristic. This is due to a resonant energy niveau in a double barrier structure realized in a heterostructure. Common heterostructures applicable for resonant tunneling diodes are III/V materials with a high bandgap discontinuity. Recently, first resonant tunneling diodes were fabricated using Si/SiGe heterostructures. The advantage of SiGe is that the compound semiconductor is grown on Sisubstrate and thus compatible to standard Silicon technology. However, most of the SiGe RTD’s do not show their negative differential resistance at room temperatur. Hence, a cryogenic characterisation of both, DC and RF has been performed at the Solid-State Electronics Department.
Cryogenic Measurement Station: The cryogenic measurement station consists of a probe chamber containing two micropositioners with high frequency probe tips capable to measure from 45 MHz up to 40 GHz. Two semi-rigid cables lead to a vacuum stable RF-interconnect where a 50 GHz Vector Network Analyzer is connected at. The DUT is fixed with conductive silver on a low-vibration probe chuck. An OpenShort-Load-Through calibration on a calibration substrate has been performed before the chamber has been air evacuated. After evacuation, the probe chuck is locally cooled down by a helium based cooling head to a minimum low temperature of ~12 K. Two silicon diodes are used to measure temperature and a heater is employed to stabilize the temperature for measurements. The whole measuremente takes about 3 hours including evacuation and cooling.
Resonant Tunneling Diode Measurements: The investigated diodes do not show a negative differential resistance region at room temperature. The first recognizable NDR has been observed at about 77 K and improves for lower temperatures until a peak-to-valley-current-ratio (PVCR) of 2 is reached at 15 K. In Figure 1 the measured DC characteristic is presented for temperatures below 60K. The diode under test had an active diode area of 50 um² and compared to InP RTDs a very low peak current density. Measurements on SiGeRTDs with smaller areas have shown that the current density decreases with active area and the peak and valley voltages move to smaller values. In addition the high impedance of the measured devices have caused problems during the high-frequency vector analysis. The output power from the test port of the Vector Network Analyzer (VNA) is limited to a minimum power of -10dBm. Lower values will cause the VNA to loose the intermediate frequency (IF) and thus cannot be
Annual Report 2005 - Solid-State Electronics Department
45
applied to the DUT. Because the applied power is still too high for high impedance devices, an additional attanuator has been used to reduce the incident power. With a 20dB attenuation, reliable s-parameter measurements have been achieved (see figure 2). But due to the fact that the reflection measurement system dynamic is reduced by twice the applied attenuation, a further reduction of power was not applicable without getting very close to the noise floor.
Figure 1
Low temperature I/V characteristic of a 50um² active area SiGe-RTD
Additionally, strong parasitics disturb the RF-measurements of the DUT. A large capacitance in parallel to the RTD causes a high-frequency drop of the applied signal (see figure 3). This can be referred to a highly n-doped SiGe-layer that is located between the Si-substrate and the SiO. That layer is used to contact the anode of the RTD but also forms a capacitance with the upper metal contact structures that influences the rf-measurements strongly. This is supported by the temperature dependence of the reflection parameter (see figure2) where a reduction of the parasitic elements can be observed at lower temperatures. At low frequencies the bias dependency of the RTD could be seen. For biasing close to the peak-current voltage a strong increase of the impedance could be observed indicating the NDR region. A biasing in the NDR region and thus the measurement of a negative differential resistance was not possible due to the high impedance of the device.
Summary: The negative resistance of SiGe resonant tunneling diodes has been demonstrated at very low temperatures down to 15°K by DC measurements. The diodes have shown a very high impedance
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Annual Report 2005 - Solid-State Electronics Department
and a large parasitic capacitance causing problems during the rf-analysis. Due to the relatively large active area of the investigated device a bias depended reflection measurement was possible at low frequencies, only. Smaller areas were not possible to measure with the network analzer. Improvements have to be done on the metallization for the RTD contacts. A reduction of the parasitic capacitance is necessary for upcoming investigations on SiGe devices.
45°K 30°K 15°K
60°K
Figure 2
Reflection parameter S11 in the Smith chart for low Temperatures from 60°K to 15°K
Si-Ge RTD Llead
Rcont_m
Rlead Cpad Rpad
Figure 3
Crtd
Rrtd
Rcont_s
Small-signal temperature dependent equivalent circuit model for SiGe RTD including pad parasitics and extrinsic contact resistances
Annual Report 2005 - Solid-State Electronics Department
4.3.2
47
InP-Heterostructure-Field Effect Transistor Parasitics Extraction
Scientist:
A. Matiss
Introduction: Parasitics from the contact structure of microwave components usually cannot be included into the calibration. Therefore, parameter extraction techniques are necessary to determine parasitic elements. This article describes the modeling technique of the parasitics of a high electron mobility transisstors (HEMT) used at the Solid-State Electronics Department.
Measurement techniques: A common method is to measure the s-parameters of an open, short, through structure and deembed the calculated two-port data from the structure containing the DUT. The structures should ideally have the same design. The restrictions of this method is that there are still differences between the test-structures and the DUT-structures. Therefore, these measurements might cause errors in modeling when applied. Other methods apply extraction techniques to determine parasitic components from specific measurements of the microwave structures with the DUT included. A common method is to drive the transistor into hot-cold states and measure the s-parameters where certain assumptions about the parasitics are possible.
Extraction of Inductances and Resistances: Curtice has proposed the hot-fet modelling technique [1] for determination of inductances and resistances for MESFET in the 1990s. At the Solid-State Electronics Department a similar technique based on Curtice model for the hot-Fet is used for HEMT. The HEMT is driven at a gate-source voltage far in the forward bias region. To eliminate any influence from drain-source currents or an intrinsic voltage drop, the drain source voltage has been set to zero. This is achieved by applying a current source that is half the current that flows into the gate. Thus, due to Kirchhoff’s law the drain current and the source current are ideally the same but with opposite polarity and thus eliminating the voltage-controlled current source and thus any current flow between the drain source region of the intrinsic transistor. The resulting small-signal equivalent circuit could be assumed as presented in figure 1. In addition to the Curtice model, the current distribution over other layers than the channel due to the high gate gate current is taken into account by adding capacitors for each contact. For the determination, genetic and gradient algorithms are used to fit the measured s-parameters to those of the equivalent circuit as presented in figure 1.
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Annual Report 2005 - Solid-State Electronics Department
LG
RG
Cdg
Cdd
Rdg
Rdd
RD
LD
G
D Cds
Rds
Cpg
Cpd RS LS
S Figure 1: Small-signal equivalent circuit of a FET for the Curtice extraction method.
S(2,2)
S(1,1)
All the intrinsic components of the HEMT can be neglected for further estimations. If the gate diode is not driven far into the forward region, the capacitance of the small-signal equivalent circuit is very large and affects the reliability of this extraction method. The figure 2 shows the measured s-parameters for high gate-currents that allows an accurate parameter extraction.
freq (45.00MHz to 40.00GHz)
Figure 2
freq (45.00MHz to 40.00GHz)
Measured and simulated s-parameter for input and output reflection coefficient.
For high gate-currents the influence of the parasitic diode capacitance decreases. Thus for a bias point high enough to neglect the diode the following equations based on a simplified equivalent circuit can be used to determine the parasitic inductances and extrinsic resistances of the structure.
Annual Report 2005 - Solid-State Electronics Department
49
RS = Re{Z12 }
LS = Im{Z 12 }/ ω
RD = Re{Z 22 } − RS
LD = Im{Z 22 }/ ω − LS
RG = Re{Z11} − RS
LG = Im{Z 11 }/ ω − LS
Pad-Capacitances Dambrine and Cappy proposed the cold-Fet technique for MESFET characterization [2]. The drainsource voltage is forced to zero volt while the gate-source voltage is set below the threshold voltage. When performing a s-parameter measurement only the capacitances should affect the measurements. The resulting admitances as seen in figure 3 only depend on the input pad capacitance Cpg and output pad capacitance Cpd and a capactiance Cb between the gate-source and gate-drain contacts under sub-threshold conditions. By applying the following equations the capacitances can be estimated: Im(Y11 ) = jω (C pg + 2C b ) Im(Y12 ) = Im(Y21 ) = − jωC b Im(Y22 ) = jω (C b + C pd ) 50 40
C / fF
Cpd 30
Cb 20
Cpg
10 0 0
5
10
15
20
25
30
35
40
freq / GHz
Figure 3
Frequency dependence of the calculated capacitances
Conclusion Extrinisic parameter estimation is necessary for the precise modeling of the intrinsic elements. The methods proposed by Curtice, Dambrine and Cappy described here have been optimized and allow an accurate estimation of the pad parasitics including the HEMT structure. The pad capacitances, inductance can be de-embedded from the measured s-parameters for more precise pregnition of transistor behaviour in circuits. The resistances mainly come from the intrinsic part of the transistors and should not be corrected for. References [1]
W.R.Curtice, “GaAs MESFET Modeling and Nonlinear CAD”, IEEE Trans. on Microwave Theory and Techniques, vol. MTT-28, pp.448-456, May 1980.
[2]
G.Dambrine et al., “A New Method for Determining the FET Small-Signal Equivalent Circuit“, IEEE Trans. On Microwave Theory and Techniques, vol. 38. 1990, p.891
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Annual Report 2005 - Solid-State Electronics Department
4.3.3
High-frequency-characterisation and modelling of HBTs
Student: Scientist:
Kai Baumann Silja Ehrich
Introduction The aim for this work is the test of the HBT´03 mask set with InP/InGaAs heterostructure-bipolartransistor (HBT) designed in the Solid-State Electronics Department in Duisburg. It has been processed to improve the high frequency performance, e.g. maximum oscillating-frequencies and transit-frequencies. Therefore, several designs in terms of crystal orientation, alignment and size are included in the mask set. The impact of these variations are analysed by DC and RF measurement. The equivalent-circuit-elements have been determined using the small-signal-model in quadripole-description as shown in figure 1 [1]. CIO Rfb
Cfb
Cjc
CBP B
LB
RB
i
Rbb RBP
ie
RC
LC
C
Rjc
Rje
Cje
CIN
intrinsic elements
RE
extrinsic elements
Rcc
COUT
i = α 0 ⋅ i e ⋅ e − jω T
LE
E
E
Figure 1: the complete small-signal-model in quadripole-description The model distinguishes between intrinsic and extrinsic elements. The intrinisic ones describe the transistor itself. They depend of the operating bias and can be displayed as a T-equivalent-circuit-
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51
diagram. The intrinsic elements are extracted by using the single bias operation. This means, that every intrinsic element depends of the its operating point. The extrinsic ones contain the contact-pads, the cables and everything around the transistor. They are independent of the operating point and their geometry and are extracted by the multi bias way. Both will be solved by the evolution-algorithm and the method of gradients. The selfaligned-HBT base-contact is closely to the emitter-mesa. The advantages of this setup are a smaller resistance RBB as well as smaller capacity Cjc formed between the base contact and the collector. Accordingly a higher maximum oscillating-frequency fmax is expected. The non-selfaligned-HBT is different in the way, that the base is farer away from the emitter-mesa. A possible advantage is a higher gain B because of less recombination under the base-contact. But on the other hand the disadvantage consist of a bigger capacity Cjc and therewith a lower maximum oscillating-frequency fmax.[3] In this way the first results extracted from DC-measurement using formula 1 show, that nonselfaligend devices reach higher DC current gain B due to their lower chance of recombination than selfaligned ones:
B=
IC IB
(1)
Cjc fF /
Cfb fF / 65 60
16
1*10 nsa
55 50
12 10
45 40
8
35
6
30
nsa
4
25
sa
20 15 20
1*10
14
30
40
50
60
70
80
2 0 20
sa 30
40
50
60
70
80
I / µA B
I / µA B
Figure 2: relation of the capacitie of selfaligned and non-selfaligned designs But on the other hand they have worse high-frequency-performance as a result of higher intrinsic capacitance-value than the selfaligned ones as calculated by following formula
f max =
fT 8π ⋅ Rbb ⋅ ( C jc + C fb )
and shown in figure 2.
(2)
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Annual Report 2005 - Solid-State Electronics Department
The different sizes are studied by establishing a small-signal-model for appointing the intrinsic equivalent-circuit-elements. By analysing this ones it is shown that it is possible to draw conclusions from the intrinsic elements to the component-design. Especially the scale of the emitter-area has a big effect to the maximum oscillating-frequency. A maximum frequency fmax of 350 GHz for small emitter-width can be achieved as depicted in figure 3. The maximum frequency is reached by a big ratio of the length to the emitter-area. fmax / GHz 350 300 250
1*15 1*10
200
1*5 150
2*10 2*15 2*5 3*10
100 50 0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
S
C
mA/µm2
Figure 3: maximum oscillating frequency of different emitter-areas
In summary, the mask-set HBT’03 means a big improvement in comparison the old mask-set HBT’97 both the high-frequency-performance and DC-current-gain as well as the yield. References: [1] [2] [3]
Dirk Peters: Modellbildung und Simulation von Heterostrukturbipolartransistoren aus III/V Halbleitermaterialien; Dissertation, Gerhard-Mercator-Universität – GH Duisburg, 1997 F. J. Tegude: Technische Elektronik 1,2; Skript zur Vorlesung, Universität Duisburg-Essen, 2004 William Liu: Fundamentals of III-V Devices, HBTs, MESFETs and HFETs/HEMTs; Wiley-Interscience, 1999
Annual Report 2005 - Solid-State Electronics Department
4.3.4
53
SPICE Simulation of Photo Receiver using PIN-RTD-HBT devices
Student: Supervisor:
W. Wang J. Driesen, W. Prost
Introduction The negative-differential resistance (NDR) characteristics of the Resonant tunnelling Diode (RTD) may be exploited to construct the Monostable Bistable transient Logic Element (MOBILE) [1], which performs logic functions at ultra-high speed. The MOBILE with a photo diode input [2] can be used as a digital photo receiver if the clock voltage is adjusted to the optical input signal. In this work it is proposed to use two optical inputs at different wavelength for data λdata and for clock λclk. Both wavelengths may be provided by a single optical fibre to staggered pin diodes. PSpice simulations of the photo receiver circuit will be presented demonstrating 10 GBits/s operation. Circuit Design The MOBILE consists of a serial connected RTD pair and a current modulator connected to the common node of the RTD pair. The output voltage Vout is a logic function of the clock voltage and the modulator current. A photo diode illuminated with λdata is used as a current modulator. We propose to add a second photo diode illuminated at a different wavelength λclk for clock generation. If the clk pin-diode is illuminated at λclk, the large photo current can adjust the clock voltage to high level. At this time, the output is controlled by the optical input for data at λdata. In Fig. 1 various functional photo receiver designs are presented with different approaches for clk generation taken from a second photo diode. Vcc2
λclk
Vcc2
Vcc1
Vcc1
1K
λclk
λdata
λdata Vclk
Vcc
λclk
λdata
T1 Vclk
1K
T1 3K
A= 5 µm2
A= 5 µm2
Vclk A= 5 µm2
Vout
Vout
Vout
A= 7 µm2
A= 7 µm2
A= 7 µm2
T2 a
Fig 1:
b
c
MOBILE-based photo receiver circuits with two optical input signals for clock (λclk) and data (λdata) with different approaches for clock generation. The clk-pin-diode is serially connected to: (a) the RTD pair, (b) the base of the HBT, (c) the collector of the HBT.
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Annual Report 2005 - Solid-State Electronics Department
Simulation and Results The device models are developed from fabricated devices at the Solid State Electronics department of the University Duisburg-Essen. The RTD model is calibrated to fulfil the characteristics of the sample M3278A_SE3 with the emitter area of 2x3.5 um² and 2x2.5 um², respectively. Two pindiodes (M3278A_SD4_PIN with 15 µm anode diameter) are utilized to receive the optical signals at the wavelength of 1.3 µm and 1.55 µm, respectively. The designs in Fig. 1 are simulated with PSpice proving the functionality of all designs. The PSpice simulation of the timing diagram of the circuit (c) is given in Fig. 2 at a clock frequency of 10 GHz. According to Fig. 2, the logic function of the gate is of AND-type since a high output voltage Vout is obtained only, if both the clk and data photo diode are illuminated.
voltage [V]
1.8
PD-signal (λdata)
Vclk
1.4 1.0 0.6
Vout
0.2 0
100
200
300
400
time [ps] Fig 2: PSpice simulation of the timing diagram of the circuit (c) at a clk frequency of 10 GHz. The functionality of circuit (c) is described in more detail. Without the optical clock signal λclk, the HBT T1 works as a base-emitter pn diode. The 1 k resistor in series to the base-emitter diode results in a high voltage drop and the clock voltage Vclk becomes low. Under illumination with λclk the transistor T1 is open due to the base current provided by the bias voltage VCC. Due to the current gain B of the transistor the base current Ib remains small in comparison to the main current through the MOBILE gate since Ib=Ic/B. The voltage drop at the 1 k resistor turns to nearly zero. Hence the clock voltage Vclk is high ( Vclk = VCC − VBE (T1 ) ) and the MOBILE output becomes sensitive to the data input at λdata. The timing diagram in Fig. 2 shows a high noise margin for the output voltage at 10 GHz clock signal. Moreover, the output levels of 0.4 V and 1.1 V fulfil the demands of input/output level compatibility. Conclusion A photo receiver for clock and data recognition is proposed. The optical signals for clock and data are provided by a single fibre but at different wavelength. By combination of RTD-, pin-, and HBT devices a functional digital AND gate is developed. PSpice simulations based on realized single devices proof its capability for 10 GBit/s operation.
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References: [1] K.Maezawa and T.Mizutani; A New Resonant Tunnelling Logic Gate Employing MonostableBistable Transition, Japanese Journal of Applied Physics, vol.32, 1993. [2] Kimikazu Sano and Koichi Murata; An 80/Gb/s Optoelectronic Delayed Flip-Flop IC Using Resonant Tunneling Diodes and Uni-Traveling-Carrier Photodiode, IEEE Journal of solid state circuits, Vol.36.No.2, February 2001.
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4.3.5
Annual Report 2005 - Solid-State Electronics Department
Optoelectronical High Frequency Characterisation of MOBILE Gates with Optical Input
Student: Scientist:
Thomas Geistert Andreas Matiss
Introduction The device under test of this work is a Monostable Bistable Transition Logical Element called MOBILE gate, which has been fabricated in the diploma thesis of Dipl.-Ing. Salim Mahmud [1]. The MOBILE gate consists of two RTDs (Resonant Tunneling Diode), where the area of the load RTD is bigger than the one of the driver RTD, and one pin diode as optical input. The circuit used in this work is employes a differential amplifier as output driver. The basic circuit and the principle switching pattern of a MOBILE gate with optical input is shown in figure 1.
Figure 1: Basic circuit and principle switching pattern of a MOBILE gate with optical input The purpose of this work is the optoelectronical high frequency characterization of these MOBILE gates. Therefore, a testboard was developed to supply the necessary DC-voltages from the back side of the testboard to the circuit which is bonded into an IC-package. The RF clock input and the RF output as well as the optical fiber for the optical input were connected to the circuit from the top. Beside this, four DC-sources were needed to bias the circuits. The optical input signal was generated by an electrical 12,5 GBit/s pattern generator. An optical modulator modulated the electrical signal from this generator to a cw-laser with the wavelength of 1550 nm. The generated optical signal was then amplified by a EDFA (Erbium Doped Fiber Amplifier). The electrical RF clock signal was also generated by the pattern generator. A 50 GHz sampling oscilloscope and an Error Detector were used to detect the output signal of the MOBILE gates. Figure 2 shows the schematic structure of the measurement station and the interconnection between the measuring devices. The device under test (DUT) is located in the center of the figure.
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Figure 2: Schematic structure of the measurement setup
Figure 3: Eye diagram taken at a data rate of 5 GHz Now, the available circuits were characterized in sequence. Eye diagrams were taken from the output signals of these two working circuits. The open eye diagram proves that MOBILE gates with optical input work up to a data rate of 5 GBit/s. Figure 3 shows an eye diagram which was recorded with this data rate. The eye opening was 80ps broad and 60mV high. The jitter both on the rising and on the falling edge of the output signal amounted to 50ps. Furthermore, it has been found that
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MOBILE gates with large RTD areas (2 x 10/12.5 µm) and large pin diodes (Ø 25 µm) show a better switching behaviour and less noise at high frequencies as gates with smaller areas. Bonding Problems During the analysis of the defective circuits it showed up that these were damaged or even destroyed by the process of bonding the integrated circuits into the IC-packages. This problem could be attributed to an electric discharge of a large capacitor which is used to melt the bonding ball at the end of the bonding wire. Under certain conditions the electric current of this discharge can flow through the device under test and destroys the circuit. The electric insulation of the pins of the IC-package against the chuck of the bonder will probably prevent the current to damage the circuit. However, this could not finally be verified due to the lack of further integrated circuits to test. Figure 4 shows one integrated circuits where the electric discharge caused destruction. One can see a melted circuit path between the pin diode and the two RTDs and some black dots on the surface of the integrated circuit. Such damages are typical for the bonding problem.
Figure 4: Micrograph of a MOBILE which was destroyed by electrical discharge during bonding Acknowledgement Sincerely thanks to the members of the Department of Optoelectronics at the University Duisburg-Essen, Campus Duisburg for their support with respect to optoelectronic measurements. References [1]
S.Mahmud, “Entwurf und Herstellung eines MOBILE-Gatters mit optischem Eingang”, Diploma Thesis, Universität Duisburg-Essen, Department of Solid-State Electronics, April 2003
Annual Report 2005 - Solid-State Electronics Department
4.3.6
59
Software development of a LABView programme for the DC and RF characterisation of Heterojunction Bipolar Transistors
Student: Scientist:
Ingo Nannen Jörn Driesen, Silja Ehrich
Introduction The rising complexity of Integrated Circuits demands an accurate DC and RF characterisation. The development and advancement of reliable and multifunctional software is therefore of high importance. Two different porgramms have been used by the research team of HLT as a standard in the past. The instant use of BASIC software for the DC measurements and Agilent Vee for RFparametrisation was rather uncomfortable. One of the disadvantages of this system was the incompatibility of both software data types. Based on the main features of both characterisation programms, the new LABView Software has been developed in order to determine both DC and RF parameters of the DUT simultaneously. Direct current and DC-Voltage supply is provided by SMU HP4142B. RF analysis is established by Analyzer HP8510C. Both devices interact via the GPIB-buss with the computer. The adjustment setting and control of the parameters is managed by diverse servo loops and subroutines implemented in the labview software. The following DC characteristic curves can be determined by the implemented measurement software. output characteristics transfer characteristic input characteristic diode characteristic gummel-plots (forward and reverse) Figure 1 shows the control panel for the DC analysis. The measured data is displayed by indicator 3. Were it is important the programme switches automatically between cartesian and logarithmic coordinates if necessary. The active values for the different voltages and currents during the measurement are displayed by indicator 5. Indicator 4 shows the progress of the measurement. The input lead resistance can be determined in order to improve the accuracy of the measurement. The voltage drop on the lead is considered by the calibration of the DC power supply by the software. The user should change the Mainpanel for RF – measurement to do a RF characterization of a transistor. The Mainpanel is shown in figure 2. The programme includes different ways to adjust an operating point as shown in indicator 12. The possibilities adjustments are:
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base current and collector – emitter voltage base –emitter voltage and the collector – emitter voltage collector current and collector – emitter voltage collector current and base – collector voltage base current and base – collector voltage Servo loops were created for the four last mentioned adjustments. The programme is able to present the results of the measurement within a Smith – Chart, amplitude – frequency – chart and phase – frequency – chart. Data can be stored in different file formats. Citifile format and HLT format used by the BASIC – programm for DC measurement are available as well as Touchstone format for data acquired by RF – measurement. References: [1]
Handbook HP 8510C Vector Analyzer
[2]
Handbook HP 4142B Parameter Analyzer
[3]
F.J. Tegude „Technische Elektronik 1,2“ Script of the lecture, 2003
[4]
F.J. Tegude „Technische Elektronik 1,2“ script of the lab, 2003
[5]
„LabVIEW7 Express“ National Instruments, 2003
[6]
HP VEE Advanced Programming Techniques Hewlett Packard, 1997
Annual Report 2005 - Solid-State Electronics Department
Figure 1.
Mainpanel for DC – measurement
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Figure 2.
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Mainpanel for HF – measurement
Annual Report 2005 - Solid-State Electronics Department
4.3.7
Student: Supervisor:
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Development of a program for visualisation and analysis of high frequency and direct current measuring data of HeteroBipolar-Transistors J. Kalender J. Driesen
Introduction Complete and time-efficient DC and RF characterisation of Hetero-Bipolar-Transistors (HBT) is an important task. This characterisation needs the visualisation of high frequency and direct current measurement data from different setups and the extraction of characteristic parameters. The following report presents a new tool developed to ease and accelerate this task. Former Measurement Procedure The usual way to analyse the data got from the DC and HF measuring stations is divided into several steps. This division is caused by the number of tools under different operating systems which are used for this purpose. Each of this tools has its own special task. Programs like the HLTExplorer, HF-View or Viewport are used for the visualisation of the measuring data in output characteristics, reverse- and the forward-gummel-plot or HF parameters like admittance, scattering, impedance and hybrid parameters in Smith Charts. Other jobs like the transformation of scattering parameters to the different HF parameters or the correction of measuring data by de-embedding are used to be done with some unix tools. The extraction of important characteristics as the transit frequency or the maximum oscillation frequency needs other tools again. This complicated and time-consuming way of characterisation is the reason to develop a new program. The aim of this work is do give an one-in-all solution to the faculty which makes the way to achieve this purpose faster and more comfortable. Realization of Measurement Analysis Tool The programming was done with Microsoft Visual Studio 6.0 containing Microsoft Foundation Class. It is used the object-oriented programming language Visual C++. This configuration makes following expansions uncomplicated due to the popularity of C++ and the object-oriented character to devide programs into methods and classes. The structure of the tool is a dialog based structure. This makes the handling quite easy because of the clear menu navigation. The use of the developed tool is fixed on Microsoft Windows. Usual features of the developed program are the visualisation of the measuring data in output characteristics, reverse- and the forward-gummel-plot or HF parameters like admittance, scattering, impedance and hybrid parameters in Smith Charts. Auxilary visualisations of gain, forward current gain |h21| and Mason's Gain U are possible, too. There are some additional features that make this program special.
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Additional Features The first additional feature mentioned here is the two-step de-embedding. This method is a certain form of correction of the measuring data. By two-step de-embedding parasitic elements like capacitances and resistances due to bonding pads or conductor wires can be de-embedded resulting the virtual measurement data of the intrinsic transistor. This correction cannot be achieved by calibration. Extra open and short measurement are necessary for de-embedding. Two-step deembedding can be done for multiple measuring data files in a row. The de-embedded measuring data are saved to the source directory with the added file extension .de. A very useful feature of this program is the automatic extraction of important characteristics like transit frequency and maximal oscillating frequency. There are different ways to determine them like linear regression or graphic extraction. The method used by this program is based on the gainbandwidth product. The used algorithm assumes a first order low pass behaviour for the small signal current gain |h21E|. It first detects the highest cut-off frequency of all chosen series of measurement. Afterwards the gain-bandwidth product is generated with a measurement frequency greater than the determined cut-off frequency and the forward current gain |h21|. Because of the choice of only one measurement frequency for all series the resulting transit frequencies have a smooth very developing.
Figure 1.
extraction of transit frequency by forward current gain
The automatic extraction of the maximum oscillation frequency is based on a modified gain bandwidth product with the measurement frequency and Mason's Gain U. The algorithm is nearly the same like one of the extraction of the transit frequency. The extracted transit frequency and maximum oscillation frequency can be saved as text file or be shown in a graph with frequency vs. current on axis.
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Figure 2,3. dialog windows of the developed program Conclusion The developed program has several advantages to other existing tools. It is easy to handle and works under Windows. The analysis is quite fast due to missing preparation of measuring data. Special features like two-step de-embedding and the automated extraction of transit frequency and maximum oscillation frequency are further great advantages. The structure of this program guarantees simple expansions. This makes the developed program to a valuable improvement of existing tools. References: [1]
F.-J. Tegude ,,Technische Elektronik 1,2“ Skript zur Vorlesung, 2003
[2]
Hewlett Packard, Application Note 95-1 „S-Parameter Techniques for Faster, More Accurate Network Design“
[3]
Jörg Berkner „Kompaktmodelle für Bipolartransistoren“ expert-verlag, 2002, ISBN: 3-8169-2085-3
[4]
David J. Kruglinski „Inside Visual C++“ Microsoft Press, 1997, ISBN: 3-86063-394-5
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4.3.8
High frequency noise measurements of circuits using an active noise source and a spectrum analyser
Student: Supervisor:
R. Tobera A. Matiss
Introduction Noise generally represents an unwanted factor which simultaneously describes the quality of a component. Therefore the characteristic of noise behaviour in integrated circuits plays an important part. Common noise measurement techniques like the s-parameter method offer values in a frequency range of 1 GHz to 18 GHz. The spectrum analyser is able to display frequencies in the range of 1 Hz to 50 GHz so it seems to be a promising device for high frequency noise measurements in the near future. As not only the high frequency behaviour, but also the RF-noise characteristic is very important for designing circuits, two measurement setups were developed in this contribution for the detection of noise parameters: The equivalent noise temperature Te, the signal to noise ratio (SNR) and the noise figure F. The results of the noise figure measurements were compared with already existing s-parameter noise figure measurements to verify the accuracy of the discussed methods. Theory Both measurement setup are presented in figure 1. The first setup consists of a signal generator (I: frequency range:100kHz to 20GHz) the Alessi Probe Station, a preamplifier which is important for the detection of the noise power and the spectrum analyser. This set-up allows the measurement of the SNR [1] which is the quotient of the signal power S and the noise power N. Furthermore it is possible to calculate the noise figure F, which is the quotient of SNRin and SNRout , whereby SNRin represents the ratio that is measured without the DUT. SNRout represents the change of the SNR due to noise that is caused by the measured DUT.
spectrum analyser signal generator
U1 /I1
SNR-measurement
U2
I DUT
II
U3
M3HF
Y-factor-method active noise source Fig. 1. Measurement setup for (I) the detection of the SNR and (II) for measurements of the Y-factor
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In figure 1 also the second measurement setup is presented that was used for the detection of the noise figure F. In this setup an active noise source (II) is used instead of the signal generator. This noise source generates a defined noise power which can be characterised by the equivalent noise temperature Te. The temperature Te is the necessary physical temperature of a given resistor R which produces the same noise power as the used noise source. For noise characterisation the Y-factor method was used to specify the equivalent noise temperature of the DUT [2]. The mathematical relation of the equivalent noise temperature of the DUT and the noise figure F that can be derived from Te are shown in the following equations with an ambient temperature T0=290 K and T1 the equivalent noise temperature of the active noise source.
T1 − YT0 Y −1 T +T F= e 0 T0
Te =
(3) (4)
Results
In this contribution noise behaviour of four samples were analysed with the above discussed methods. This were the heterojunction field-effect transistors (DU773), the double-heterojunctionbipolar transistor (M2747-1), the single-heterojunction-bipolar transistor (M3087C) and the on HBT-technology based transimpedance-amplifier (M3297d). The results of the noise figure F is shown in figure 2 for the frequency range of 1GHz to 12 GHz. M3297d
14
M2747-1 DU773
noise figure F / dB
12
M3087C
10 8 6 4 2 1
2
3
4
5 6 7 8 Frequency f / GHz
9
10
11
12
Fig. 2. The noise figure F of all measured DUT’s
In figure 2 it is showen that the noise figure F has an almost constant behaviour up to the frequency of 12 GHz. The TIA M3297d has the highest noise figure for high frequencies because it was not designed for frequencies above 10 GHz and has a 3dB-frequency for f3dB = 9 GHz. The gain of this component decreases for higher frequencies. At the same time the noise generated by the TIA rises as can be noticed in figure 2. The HFET (DU773) shows the lowest noise parameters which is generally typical for these components. The DHBT shows a noise figure twice as high compared to the SHBT.
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In order to analyse if the measuring method are appropriate for accurate determination of noise, the results were compared with s-parameter noise measurements of the same DUTs that were recorded in the Solid-State Electronics Department before. In figure 3 the minimum noise figures Fmin are compared with the results of the Y-factor method. For both samples the same operating points were chosen as for the s-parameter noise measurements. 16 M2747-1
noise figure F / dB
14
Fmin/M2747-1 M3087C
12
Fmin/M3087C
10 8 6 4 2 2
3
4
5
6
7
8
9
10
11
12
Frequency f / GHz
Fig. 3.
The noise figures of the components M2747-1 and M3087C measured with the y-factormethod are each compared with their Fmin
In figure 3 it can be observed that both measured HBTs show a higher noise figure characteristic than the corresponding Fmin. The reason for this behaviour is the fact that both samples were measured in a 50 Ohm environment. For frequencies above 12GHz the difference between both graphs becomes more obvious. This is due to the preamplifier M3HF that has a drop of gain for higher frequencies that results in a loss of measurement accuracy. Conclusion
The spectrum analyser is generally a suitable device for high frequency noise measurements of electrical components. The Y-factor method can be used for noise measurements up to 18 GHz. This is the maximum frequency for which the active noise source is able to produce a defined white noise power. The SNR-measurement allows noise characteristic up to a frequency of 20 GHz (it is the maximum frequency of the generator).
References [1]
[2]
K. Solbach, „Noise characterization of two-port networks“ Praktikum Universität Duisburg-Essen, 2005 Rafael Bednorz, „Re-Design eines 40GHz Breitbandverstärkers auf Basis eines HBT-Schichtsystems“ Diplomarbeit, Universität Duisburg - Essen, 2003
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4.3.9
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Automated Characterisation of power amplifiers for 3GWCDMA mobile communication systems for evaluating predistortion techniques
Student: Supervisor: Industrial Supervisors:
cand. ing. Johannes Henze Dr. W. Brockerhoff, Dr. E. Busheri, limemicrosystems, Prof. Ali A. Rezazadeh, University of Manchester
Introduction Modern wireless Base Stations (BTS) and mobile handsets require high efficiency Power Amplifiers (PA). High efficiency PA results in direct saving of BTS running costs and provides longer battery life for handsets. However the efficient operating point of PA lies in the nonlinear region, where harmonics and intermodulation frequencies are most prevalent. Particularly in non constant envelope modulated signals such as 3G-WCDMA, it is essential to back-off the PA at the cost of reducing the efficiency so as to lower the magnitude of these harmonics. To alleviate this problem, the nonlinear characteristics of the PA can also be compensated using a number of linearization techniques. In this context, the PA and distorter characterization is of paramount importance. Hence the objective of this project was to establish a quick and automated means for the evaluation of PA and linearization techniques. This was achieved using different PA excitations. The different setups will now be described. Continuous wave excitation The continuous wave measurement setup developed during this work is intended for the simple measurement of AM/AM and AM/PM characteristics of PA. To obtain absolute power values from the Vector Network Analyser used, a power flatness calibration was performed. A preamplifier was used during calibration to obtain the high power levels needed to drive the DUT into compression. Figure 1 shows the measurement setup used to measure the AM/AM, AM/PM characteristics of an LDMOS PA shown in Figure 2. E4418B power meter
internal GBPIB BUS
8487A power sensor
PORT 1
VNA
PORT 2
GPIB
85107A Test Set
preamplifier
Figure 1.
HP-VEE data aquisition PC
DUT
30 dB attenuator
Continuous wave measurement setup. The dotted lines show the connections necessary for calibration.
70
Figure 2.
Annual Report 2005 - Solid-State Electronics Department
Measured AM/AM and AM/PM characteristics of an LDMOS PA
The maximum linear drive power sweep range (0 to 25dBm @ 2GHz) decreases at higher frequencies due to increasing attenuation in the test set. The gain decrease and increase at higher RF input powers in Figure 2 can be explained by the generation of new frequencies. Power is transferred to harmonic frequencies causing the gain change. To evaluate this effect, the excitation with two tones is valueable. The next section shows this measurement method. Two tone excitation To measure the generation of new frequency components in the RF output of PA or predistortion devices, due to nonlinear transfer characteristics, a measurement in the frequency domain is necessary. This has been realized using a HP 8565E spectrum analyser, signal generators, filtering and preamplification as well as a wilkinson power combiner. The optimum measurement configuration has been determined through test measurements while the input attenuation is adjusted by the limemicrosystems control software. Figure 3 shows the developed measurement setup which had a residual third order intermodulation ratio (IMD3) of 85dBc at a maximum drive power of 25dBm. The developed setup has been used for the evaluation of the before mentioned LDMOS PA. Intermodulation sweet spots at specific bias voltages as well as RF-input power levels have been identified. Figure 4 shows the measured data and the outcome of a simple polynomial model which can be used to explain the occurrence of sweet spots.
Annual Report 2005 - Solid-State Electronics Department
GPIB BUS
71
GPIB BUS E3641A DC power supply limemicrosystems control software
PC BIAS1
Marconi 6200
E3641A DC power supply
BIAS2 HP8565E E4438C ESG Vector Signal Generator DUT
10 MHz reference frequency
2nd harmonic filters
minicircuits preamplifiers
2nd harmonic filters
Figure 3.
Developed automatic two tone measurement setup
Figure 4.
LDMOS PA intermodulation measurements
power combiner
WCDMA excitation In order to gain information about the real performance of a given PA or predistorter design the testsignal used has to be comparable to the communication signal which will be amplified. To make this final test possible, a WCDMA basestation signal has been simulated in ADS and then modulated on the RF carrier using a vector signal generator. A vector signal analyser was used to measure Adjacent Channel Leakage Ratio (ACLR); Error Vector Magnitude (EVM) as well as the Cumulative Complementary Distribution Function (CCDF). The measurement setup shown in Figure 5 is controlled by a HP-VEE program written to aquire measurement data, control bias voltages and measurement settings. To obtain the minimum possible residual ACLR the input attenuation value of the vector signal analyser is set by the program using a new developed algorithm. The residual ACLR of 55dBc (at 10dBm average drive power) was limited by the noise
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floor of the equipment used. At higher power levels the residual ACLR deteriorated due to compression in the preamplifier. DUT
modulated RF signal E4438C ESG Vector Signal Generator
preamplifier DC voltage and current data via GPIB
HP-VEE program
I/Q data via GPIB
Figure 5.
PC
measured samples and commands via firewire
bias2
attenuation
bias1
95MSa/s input VXI to down ADC firewire calibratio converter filter n module FIFO
INPUT
E3641A DC power supply
E8491B 89605A E2730A E1439A
VXI-mainframe
896400 Vector Signal Analyser E3641A DC power supply
WCDMA measurement setup
Acknowledgement Thanks to limemicrosystems company and the members of the electromagnetics centre (University of Manchester) for making this project possible as well as for valuable discussions.
Annual Report 2005 - Solid-State Electronics Department
4.3.10
73
Detailed analysis of a fully integrated voltage-controlled differential Colpitts-oscillator
Student: Supervisor:
A.Viessmann J. Driesen, F. Damitz
Introduction The limited availability of free frequency bands and the great licensing-costs involved force the semiconductor manufacturers to decrease the (sub-) channel distances in communication systems in order to achieve a further increase of the netto bandwidth. There is an increasing demand for oscillators with higher spectral purity and therefore lower phase-noise, avoiding resulting perturbations between adjacent channels. The differential Colpitts-oscillator is the subject of this diploma thesis carried out at ATMEL Duisburg GmbH, Germany. Three variants of this oscillator are manufactured in the commercially available Atmel 0.35µm SiGe-BiCMOS AT46k process. The results of simulations and measurements are compared to the commonly used cross-coupled oscillator. The major criterion is the phase noise which describes the spectral purity of oscillators and presents a limiting factor according to the realisation of communication systems. Further criterions are current consumption, output frequency, tuning range, input and output power and the required chip area. Oscillator topologies
L1
R2
R1
L2
C2
C1 Q1
Q2 IBias
Figure 1: The cross-coupled oscillator
Figure 1 shows the cross-coupled oscillator which mainly consists of a differential amplifier made up of the two transistors Q1 and Q2 and the current source. The inputs of this circuit are cross coupled with the outputs to enable oscillation. The main advantage of this oscillator-type is the presence of only one current source. The power consumption is very low. For this reason this oscillator type is interesting for mobile applications. A further benefit is its ease of implementation in different technologies as well as achieving a great tuning range. The variable capacity completely results in a frequency change.
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L1
L2 Cvar
C1
T1
T2
IBias
C2
C2
C1
IBias
Figure 2: The differential Colpitts-oscillator in common base configuration Figure 2 shows the differential Colpitts-oscillator in a common base configuration. The key structure element for the Colpitts-oscillator is the capacitive feedback of the output signal to the input of the circuit. Although the output signal can be obtained at the collector, it is feeded out at the node between the capacitors C1 and C2. This leads to two important advantages. First of all, the input resistance of the amplifier in common base configuration is tranformed to a higher value. Thus the resonator has a lower load, and the quality factor decreases insignificantly. Additionally, the input resistances of the following stages are transformed to a higher value. And secondly, the output driver load pulling effects - which describe a decrease of the oscillator properties because of load changes - are suppressed. Disadvantageous is the need for two current sources, which leads to higher current consumption compared to the cross coupled oscillator. The reason is that the differential Colpitts-oscillator is a combination of two single-ended oscillators, which are coupled by the capacitor C2. Another disadvantage is the restricted tuning range of the differential Colpitts Oscillator. Because of the series connection of the variable capacitor to capacitors C1 and C2, a change of the variable capacitor causes only a fraction of output frequency change compared to the cross coupled oscillator. Measurement results Figure 3 shows the phase-noise measurement of the differential Colpitts-oscillator in comparison to the cross-coupled oscillator. The phase-noise is measured in 100 kHz offset to the corresponding carrier in dependence of the overall current consumption of the circuit. The bias currents of the transistors in the Colpitts-oscillator may be varied which makes the examination of the oscillator in dependence of the transistor properties possible. There is no mechanism to change the bias points in the cross-coupled oscillator, because of this the phase noise is drawn current independent. As the theroy of impuls sensitivity function predicts, a lower phase noise is measured at the Colpitts-oscillator in comparison the cross coupled oscillator. With decreasing frequency the phase
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noise increases because of the lower tank quality factor. There is a current dependent phase-noise optimum in which the transistors shows a good relation between noise and gain. With further increasing of the bias current the gain decreases while the shot noise increases. This leads to a higher phase noise.
α{f0+100kHz} /
dBc Hz
-84
Colpitts oscillator; f0=5,168 GHz Colpitts oscillator; DEC=32; f0=4,75 GHz
-86
Colpitts oscillator; DEC=63; f0=4,42 GHz Cross-coupled oscillator
-88 -90 -92 -94 -96 -98 41
42
43
44
45
I / mA
Figure 3: Current dependent phase noise of the Colpitts- and the cross coupled oscillator Conclusion The Colpitts-Oscillator shows a very good phase noise of -98 dBc/Hz in 100 kHz offset to a 4.8 GHz carrier in comparison to the -88.5 dBc/Hz of the cross-coupled oscillator. On the other hand, in comparison to the cross coupled oscillator, the Colpitts oscillator shows an increased need of chip area by 50 %. This is caused by the greater variable capacitor which have to be chosen in order to get a similar tuning range. The DC input power is increased by 100%. Acknowledgement Thanks to ATMEL Duisburg GmbH for making this project possible as well as for valuable discussions. The results of this work have also been published in the Digest of Papers, IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems 2006, pp. 182-185. References: [1] [2]
J. Rogers, C. Plett; “Radio Frequency Integrated Circuit Design”, Artech House, Boston, London, 2003 A.P. Brokaw; “A Simple Three-Terminal IC Bandgap Reference”, IEEE Journal of Solid-State Circuits, VOL. SC-9, NO.6, December 1974, pp 388-393
76 [3] [4] [5] [6]
Annual Report 2005 - Solid-State Electronics Department A. Hajimiri, T.H. Lee; “A General Theory of Phase Noise in Electrical Oscillators”, IEEE Journal of Solid-State Circuits, VOL. 33, NO.2, February 1998, pp 179-194 A. Hajimiri, T.H. Lee; “Low Noise Oscillators” Kluwer Academic Publishers, 2000 A. Hajimiri, T.H. Lee; “A General Theory of Phase Noise in Electrical Oscillators” IEEE Journal of Solid-State Circuits, VOL. 33, NO.2, February 1998, pp 179-194 R. Aparicio, A. Hajimiri; “A Noise-Shifting Differential Colpitts VCO”, IEEE Journal of Solid-State Circuits, VOL. 37, NO.12, December 2002, pp 1728-1736
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4.4 Nanoelectronics
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4.4.1 Scientist:
Annual Report 2005- Solid-State Electronics Department
Composition Control in MOVPE-Grown InGaAs Nanowhiskers Ingo Regolin
Introduction Semiconductor nanowhiskers have attracted much attention in recent years. Based on the VapourLiquid-Solid (VLS) growth mechanism [1], the growth of various semiconductor nanowhiskers has been reported by different growth techniques. An important feature of the VLS growth mechanism is the limitation of the growth area by the lateral size of a seed particle, that enables the fabrication of highly mismatched semiconductor structures. Despite a successful demonstration of elementary and binary nanowhiskers with atomically sharp heterointerfaces [2], there is a lack of growth experiments dedicated to the fabrication of ternary materials allowing band gap engineering. In this work we report the fabrication of InGaAs nanowhiskers on (111)B GaAs substrate with the composition controlled by supply of TMIn and TEGa. The composition, structure and the lattice parameter of the grown structures were determined by HR-XRD measurements and by HR-TEM measurements. Additionally, we observed the growth of a three-dimensional InGaAs layer whose appearance strongly depends on the composition and coverage density of nanowhisker structures. PL measurements provided first information about optical properties of realised nanowhiskers. Experimental Setup Nanoparticles were deposited on the (111)B GaAs substrate by dropping a small amount of a colloidal solution onto the substrate and evaporating the solvent. After that, the samples were annealed under N2 atmosphere at 300°C for 300 seconds in order to remove organic residuals. Investigated nanowhiskers were grown by metal-organic vapour-phase epitaxy (MOVPE). Triethylgallium (TEGa) and Trimethyindium (TMIn) were used as group-III precursor. As group-V precursor, Tertiarybutylarsine (TBAs) was used. After annealing the GaAs substrate at 600 °C for 10 minutes, the growth temperature of Tg = 420 °C was adjusted. The growth was carried out at a total pressure of 50 mbar and a total gas flow of 3.4 l/min, respectively. In all experiments the TBAs flow was kept constant, whereas the TMIn/(TMIn+TEGa) ratio was varied between 0.452 and 0.038 resulting in the variation of the V/III ratio between 5 and 10. The growth time was chosen between 5 min and 10 min. The characterisation of the grown structures was done by a combination of scanning electron microscopy (SEM), high-resolution x-ray diffractometry (HR-XRD), high-resolution transmission electron microscopy (HR-TEM), and photoluminescence (PL). Results Figure 1 presents a SEM micrograph of InGaAs whiskers grown at the TMIn/(TMIn+TEGa) ratio of 0.074. Au particles at the top of whisker struktures as well as a lot of tiny hillogs on the whiskerfree area can be resolved. A preferential growth along the [111] direction perpendicular to the substrate surface is clearly observed. However, some whiskers kink i.e. change the growth direction spontaneously. Figure 2 shows XRD rocking curve of two samples with (sample “a”) and without (sample “b”) nanowhiskers. Both samples were grown simultaneously with a TMIn/(TMIn+TEGa) ratio of 0.074.
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Sample “a” consists of whiskers structures with a density of 109 cm-2, whereas sample “b” was grown without seed particles. The presence of nanowhiskers as well as a three-dimensional InGaAs layer clearly appears in XRD spectra.
Figure 1. SEM micrograph of InGaAs nanowhisker grown on GaAs substrate Beside the GaAs substrate peak at 27.301°, sample “b” shows one additional broad peak, which may originate from a thin InGaAs layer with a In concentration of 18.8 %, only. Oppositely, the XRD rocking curve of sample “a” has two additional peaks that will be attributed to the nanowhiskers and the 3-dimensional layer, respectively. We attribute the higher and sharper peak to the fabricated nanowhiskers [3]. Compared to sample “b”, the In concentration in the whisker structures is somewhat lower with 16.4 %. It means that the incorporation of Ga atoms at the liquidsolid interface as well as the transfer through or on the liquid alloy is, in general, faster than this one for In atoms. The peak related to the 3-dimensionl layer is lower and wider because of a relatively high density of whiskers (~109 cm-2) collecting most of the source material. In addition, an indium concentration of 26 % in the 3-dimensional layer is 10 % higher than in the whisker structures. It confirms the assumption about a preferred incorporation of Ga atoms into nanowhiskers.
GaAs Substrate
intensity (a.u.) [log]
whisker InGaAs layer
a) b)
25
25.5
26
26.5
InGaAs layer
27
27.5
28
angle 2Θ [°]
Figure 2. HR-XRD rocking curve of a sample with InGaAs nanowhiskers(a) and without them(b). To realise nanowhiskers with various InGaAs composition, growth runs with TMIn/(TMIn+TEGa) ratio of 0.038, 0.074, 0.137, 0.292 and 0.452 were carried out. Figure 3 shows XRD rocking curves of fabricated structures.
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The whisker peaks and the 3-dimensional InGaAs layer peaks can be clearly resolved. Depending on the chosen TMIn/(TMIn+TEGa) ratio, the peaks shift between the GaAs peak at 27.301° and the InAs peak at 25.444°. From the position of the whisker peak, a corresponding indium concentration of 14 %, 16.4 %, 27.6 %, 54.3 % and 88.6 % was calculated using a linear correlation between the peak position and the material composition.
TMIn/(TMIn+TEGa) = 0.038 0.074
0.137 0.292
0.452
Figure 3. XRD rocking curves of InGaAs nanowhisker structures grown using various TMIn/(TMIn+TEGa) ratio. Verification of the evaluated whisker composition was done by direct determination of the crystal lattice constant using HR-TEM measurements. From the measured whisker lattice plane constant d111 = (0.3321 ± 0.017) nm as given from the bright field image, an fcc lattice parameter of a = 0.5751 nm was determined. This value well agrees with a = 0.576 nm calculated from the HR-XRD measurements results. Using these data, an indium concentration of 27.6 % was calculated using Vegards law that which well agrees with the concentration obtained from the XRD spectra. First optical investigations of fabricated samples demonstrated photoluminescence at ~ 917 nm originated from nanowhisker structures which corresponds to the band gap energy for the given material composition with a In concentration of 14 %. Acknowledgement The shown HR-TEM measurements were done by D. Sudfeld. This work was also supported by Sonderforschungsbereich 445 “Nanoparticles from the gas-phase” References [1]
R. S. Wagner, W. C. Ellis,“ Vapor-Liquid-Solid Mechanism of Single Crystal Growth”, Applied Physics Letters, Vol. 4, No. 5, March 1964
[2]
M. T. Björk, B. J. Ohlsson, T. Sass, A. I. Persson, C. Thelander, M. H. Magnusson, K. Deppert, L. R. Wallenberg, and L. Samuelson, Appl. Phys. Lett., 80, 1058 (2002).
[3]
I. Regolin, V.Khorenko, D. Sudfeld, W. Prost, J. Kästner, G. Dumpich and F. J. Tegude, Journal of Applied Physics, accepted (2005).
Annual Report 2005- Solid-State Electronics Department
4.4.2 Scientist:
81
GaAs Whiskers Grown by MOVPE Using Fe Nanoparticles Ingo Regolin
Introduction Since last decade, semiconductor nanowhiskers excite a great research interest due to their intriguing growth features as well as a potential application in nanoscaled electronic and optoelectronic devices. Based on the Vapour-Liquid-Solid (VLS) growth mechanism [1], the growth of III-V and group-IV semiconductor nanowhiskers has been reported by different growth techniques. Despite a successful demonstration of III/V nanowhiskers grown by MOVPE using Au particles, there is a lack of growth experiments dedicated to the fabrication of nanostructures using alternative metals. This may help to investigate the growth mechanism, which is quite not understood in detail today. Also magnetic materials could open a large field for spintronic applications like spin injection into the semiconductor whisker structures. In addition, the integration of optical features into the silicon technology instructs to replace the Au assisted growth. In this contribution we report the fabrication of GaAs nanowhiskers on (111)B GaAs substrate using Fe particles as growth seed. The structure and the lattice parameter of the grown whisker structures were determined by high-resolution transmission electron microscopy (HR-TEM) measurements. EDX analyses show clearly the presence of iron at the whisker tops and no incorporation of iron into the whisker structure during the growth. The growth mechanism will be discussed, especially compared to the VLS growth mode, where Au is normally used. Experimental Setup Since the whisker diameter will be defined by the size of a seed particle, monodisperse super paramagnetic Fe nanoparticles with a diameter of 10 nm were deposited on the (111)B GaAs substrate from the gas phase. Investigated nanowhiskers were grown by metal-organic vapour-phase epitaxy (MOVPE). The growth experiments were performed in an AIX200 RF low-pressure MOVPE system with a full non-gaseous source configuration. Trimethylgallium (TMGa) was used as group-III precursor, while tertiarybutylarsine (TBAs) was used as group-V precursor. After annealing the GaAs substrate at 600 °C for 10 minutes, the temperature was ramped down to the growth temperature, which was varied between 480 °C and 520 °C. The whisker growth was carried out at a total pressure of 50 mbar and a total gas flow of 3.4 l/min, respectively, whereas the V/III ratio of 5 was kept constant. The growth time was 15 min in all experiments. The characterisation of fabricated nanowhsiker structures was done by a combination of scanning electron microscopy (SEM) and HR-TEM. Results Figure 1 (a-c) presents SEM micrographs of GaAs whiskers grown at different temperatures. The structures shown in (a) were grown at 480 °C, (b) at 500 °C and (c) at 520 °C. Fe particles at the top of whisker structures could not be resolved in these views, because in the limitation of resolution. A preferential growth along the [111] direction perpendicular to the substrate surface could not be observed in the whole temperature range.
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On the contrary, the whisker structures were growing in [100] as well as in [110] and equivalent directions when the temperature was adjusted above 500 °C. However, with decreasing the growth temperature, whiskers kink i.e. change the growth direction spontaneously.
b)
a)
c)
Figure 1. SEM micrographs of GaAs nanowhisker grown on GaAs substrate using Fe particles as seed at different temperatures. a) 480 °C, b) 500°C, c) 520 °C In order to prevent the defect formation in GaAs whiskers completely, a temperature increase up to 520°C is necessary, whereas GaAs whiskers grown with Au are mostly defect-free at temperatures around 470°C. In addition, figure 1 shows that a strong 2-dimensional growth takes place at the used temperatures, which are necessary for the oriented growth. This 2-dimensional growth is not depending on the material, which is used as seed particle. That means this additional growth occurs at temperatures above 500 °C when TMGa is used. As a result, the additional effect of tapering and oriented growth cannot be suppressed, when TMGa is used in combination with Fe as growth seed. Compared to the VLS growth mechanism, where the whisker growth is preferred in [111] direction, the [100] direction may led to a perpendicular growth on (100) oriented surfaces, even on silicon. 1600
Fe
Intensität [b.E.]
1400 1200
Fekα1 Askα1 Gakα1 Okα1
1000 800 600 400 200 0
0
5
10 15 20 25 EDX line scan [nm]
30
35
Figure 2. TEM brightfield image of the upper whisker region including the Fe paritcle and related EDS line scan along the shown arrow.
A TEM micrograph in figure 2 shows the upper region of a whisker top. A semi-spherical iron seed particle as well as the crystal planes perpendicular to the direction has been recognized.
Annual Report 2005- Solid-State Electronics Department
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Preliminary EDX measurements confirmed the presence of Fe at the whisker top, too. A line scan of the top region is given in figure 3, which also indicates, that there is Fe at the whisker top. In addition iron can be also measured within the first 20 nm underneath the whisker top. These results indicate, that there is a similarly growth compared to the VLS mechanism where the Au droplet rides atop the whisker structure, although there is no liquid alloy in our experiments. Even at high Ga concentrations in the Au seed particle, a temperature above the here used growth temperatures is necessary to get a liquide droplet. This indicates that growth procedure is driven by a vapour-solid-solid (VSS) mechanism, when Fe is used. An additional hint for a (VSS) growth is the reduced growth rate compared to the (VLS) growth. 4. Conclusion In summary, we demonstrated GaAs nanowhiskers grown on (111)B GaAs substrate using Fe nanoparticles deposited from the vapour phase. In contrast to the VLS mecanism, where the [111] direction is preferred, the structures were growing in [100] direction in our experiments. Because of the used growth temperatures, we assume that the grown process is driven by a vapour-solid-solid (VSS) mechanism. The presence of iron at the whisker top as well as the lattice constant of GaAs was investigated by HR-TEM measurements. Like in the VLS growth mechanism, where Au particles were used, the Fe particles riding atop the whisker structures during the growth. Because of the higher growth temperature, which is necessary to create kinkfree structures, a strong tapering effect appears and the growth rate along the preferred [100] direction decreases. This is due to the 2-dimensional growth, which becomes more and more significant in these temperature ranges. To create non-tapered structures, using Fe particles, a Ga precursor with a lower cracking efficient has to be used to prevent the 2-dimensional growth up to around 550 °C. Acknowledgement The shown HR-TEM measurements were done by D. Sudfeld, while the Fe particles were provided by K. Hitzbleck and H. Wiggers. This work was also supported by Sonderforschungsbereich 445 “Nanoparticles from the gas-phase” References [1]
R. S. Wagner, W. C. Ellis,“ Vapor-Liquid-Solid Mechanism of Single Crystal Growth”, Applied Physics Letters, Vol. 4, No. 5, March 1964
84
4.4.3
Annual Report 2005 - Solid-State Electronics Department
Fabrication and electrical characteristics of n-InAs single nanowhisker field-effect transistors
Scientist:
Q. T. Do, I. Regolin
Introduction Since the last two decades, quasi-one-dimensional structures attract an increasing research interest due to their remarkable electronic properties and the potential applicability as core elements for nanoscale electronic devices. However, the top-down fabrication of these devices require nanometer precision resulting in an extreme effort for lithography and patterning. On the other hand, III/V semiconductor nanowhiskers1-2 (NWs) artificially grown using a seed particle allows to achieve it all by the growth process only. In this contribution, we demonstrate results of an electrical characterisation of n-type doped InAs NWs contacted using e-beam lithography pattern. Finally, a field-effect transistor (FET), as one of the most fundamental and important electric components, has been fabricated using an n-InAs nanowhisker. We grew InAs nanowhiskers on InAs (001) substrates by employing low-pressure metal-organic vapour phase (MOVPE) epitaxy with N2 as a carrier gas and tertiarybuthylarsin as group-V precursor. Trimethylindium was used as group-III precursor while ditertiarybutylsilane (DitBuSi) was used for the n-type doping. As seed particles were used colloidal Au nanoparticles of 100 nm in diameter deposited on the substrate surface prior to the growth. The growth experiments were performed at 400°C for 10 minutes with a constant V/III ratio of 6 [fig.1].
Fig.1. A SEM micrograph of InAs whiskers grown on InAs at 400°C with 10 µm length maximum.
Annual Report 2004 - Solid-State Electronics Department
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InAs whisker FETs were fabricated by removing the whiskers from the substrate in a isopropanol solution and their deposition on another carrier substrate followed by e-beam lithography. The carrier substrate was covered by a silicon nitride (SiN4) with a thickness of 400 nm for electrical isolation and then metal grid mask by e-beam lithography and contact pads by optical lithography. A continuous bottom-gate metal was buried in the silicon nitride layer in 100 nm from the layer top. InAs nanowhiskers removed from the growth substrate were poured onto prepared carrier substrate. Ohmic contacts were defined by e-beam lithography following by Ni/Ge/Ni/Au metal deposition. Source and Drain electrodes were annealed at 360°C for 30 sec. Finally, a protective silicon nitride layer was deposited by PECVD [fig.2].
(a)
(b)
Fig. 2
InAs single nanowhisker FET: (a) Schematic configuration of a device (b) SEM micrograph of a contacted InAs whisker covered with 250 nm SiNx.
Figure (3) shows a typical output characteristics ID = f(VDS, VGS) of a of a single n-InAs NW FET with a diameter 120 nm. The gate length of the device corresponds to the drain-source spacing of LG = LDS = 3.8 µm. At high gate bias (VGS = 0.4 V) a drain current of 90 µA is obtained corresponding to a current density in the wire of 7.9 x 105 A/cm2. The measured maximum transconductance of the FET is gm = 110 µS. Hence the normalized transconductance gm/wg = gm/d = 895 mS/mm. It is worth noting that this very high transconductance value has been achieved with a 150 nm thick SiNX dielectric layer such that ever further improvements will be easily obtained.
60
0.4
VGS/V
0.0
40
-0.2 -0.4
20 0 0.0
-0.8
0.2
0.4
0.6
0.8
drain-source Voltage VDS [V]
Fig. 3
1.0
800 600
b) InAs NW VDS = 1 V
800
gm/WG
600
400
400 ID/WG
200 0 -0.8
200
-0.6
-0.4
-0.2
0
0.2
0.4
drain current ID ** [ mA/mm]
80
1000
1000
a) InAs NW D = WG = 120 nm LDS =LG = 3.8 µm VT = -1.32 V
transcondcutance gm ** [ mS/mm]
drain-current ID / µA
100
0
gate-source voltage VGS [V]
I-V characteristics of a single InAs nanowire field-effect transistor with a wire length of 3.80 µm and a wire diameter of 120 nm: (a) output characteristics and (b) transfer characteristics.
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Annual Report 2005 - Solid-State Electronics Department
On the other hand, both the pinch-off and the saturation behaviour of the n-InAs NW FET has to be improved substantially. We further analyzed the carrier mobility (µ) in n-InAs NW FET. Assuming the device be treated like a MOSFET in the low field regime of the device holds (Eq. (1))3,
µ=
g m × L2 C × VSD
(1)
where C is capacitance given by Eq. (2) for cylinders using an infinite plate model,4 C=
2πεε 0 L ln(2h / r )
(2).
Hence, Eq. (1) can be written as
µ=
g m × L × ln(2h / r ) 2πεε 0 × VSD
(3)
where L is the channel length, r the nanowhisker radius, and h the thickness of the silicon nitride. The field effect mobility estimated from transconductance exhibits a maximum value of 4800 cm2/Vs. High-performance nanoscale FETs obtained in this work show the feasibility of III/V semiconductor nanowhiskers for electronic nanodevice applications.
Acknowledgement This work is supported by Sonderforschungsbereich SFB445 “Nanoparticles from the gas-phase”
References: [1] R. S. Wagner and W. C. Ellis, Appl. Phys. Lett., 4, 89 (1964) [2] K. Hiruma, et al., J. Appl. Phys., 77, 447 (1994) [3] S.M. Sze, Physics of Semiconductor Devices, (1981) [4] R.Martel et al., Appl. Phys. Lett., 73, 2447 (1998)
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4.5 Conference Contributions 1.
REGOLIN, Q. T. DO, V. KHORENKO, S. NEUMANN, H. WIGGERS1, W. PROST, F.-J. TEGUDE 1
: Inst. of Combustion and Gasdynamics, University of Duisburg-Essen, Duisburg, Germany
Electronic and Optoelectronic Properties of III/V Nanowhiskers grown on III/V and Silicon Substrates Nanoelectronic Days 2005, Forschungszentrum Jülich, 9.-11.02.2005
2.
Q. T. DO, T. MÜLLER, A. LORKE1, F.-J. TEGUDE 1:
Dept. of Experimental Physics, University Duisburg-Essen
Selfgating Effect in a Novel Nanometer-Scale Semiconductor Device Utilizing an Asymmetric 2-DEG Channel Nanoelectronic Days 2005, Forschungszentrum Jülich, 9.-11.02.2005
3.
W. PROST
Tunneldioden auf Silizium-Substraten – Bauelemente, Schaltungen und Anwendungspotenzial eingeladener Seminarvortrag am IHP-Innovations for high performance microelectronics, Frankfurt 23.02.2005.
4.
A.MATISS, J.DRIESEN, S.EHRICH,W.PROST, F.-J.TEGUDE
Bias Dependent Boolean Multivalue Logic Application of Resonant Tunneling Bipolar Transistors German Microwave Conference 2005 (GMC), Ulm, 05.-07.04.2005.
5.
W. PROST, P. KELLY1, A. GUTTZEIT2, V. KHORENKO, E. KHORENKO, A. MATISS, J. DRIESEN, A.MOFOR2, A.BAKIN2, S. NEUMANN, M. MC GINNITY1, A. SCHLACHETZKI2, AND F.-J. TEGUDE 1: 2:
Intelligent Systems Engineering Laboratory, University of Ulster, Londonderry, U.K. Inst. for Semiconductor Technology, Technical University Braunschweig
Design and Modelling of a III/V MOBILE-Gate with Optical Input on a Silicon substrate, 17th Int. Conf. on InP and Related Materials (IPRM), 08.-12.05.2005, Glasgow, U.K.
6.
V. KHORENKO, I. REGOLIN, S. NEUMANN, Q. T. DO, W. PROST, AND F.-J. TEGUDE
Characterisation of GaAs nanowhiskers grown on GaAs and Si substrates, 17th Int. Conf. on InP and Related Materials (IPRM), 08.-12.05.2005, Glasgow, U.K.
7.
J. DRIESEN, S. TOPLAOGLU, F.-J. TEGUDE
Optimizing Lateral HBT Design by Utilizing Perfomance Estimations 17th Int. Conf. on InP and Related Materials (IPRM), 08.-12.05.2005, Glasgow, U.K.
8.
S.TOPLAOGLU, J.DRIESEN, A.PLOCZEK, F.-J.TEGUDE
Fabrication of Transferred-Substrate HBT with Simple Technology 17th Int. Conf. on InP and Related Materials (IPRM), 08.-12.05.2005, Glasgow, U.K.
9.
W. PROST
Tunneldioden für digitale Schaltungen reduzierter Komplexität Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik im VDE/VDI: GMM-Workshop "Devices nach CMOS", München 16.06.2005.
88 10.
Annual Report 2005 - Solid-State Electronics Department W. PROST, V. KHORENKO, P. KELLY1, A.-C. MOFOR2, S. NEUMANN, A. POLOCZEK, A. BRENNEMANN, A. MATISS, A. BAKIN2, A. STÖHR3, D. JÄGER3, M. MCGINNITY1, A. SCHLACHETZKI2, F.-J. TEGUDE 1:
Intelligent Systems Engineering Laboratory, University of Ulster, Londonderry, U.K. Inst. for Semiconductor Technology, Technical University Braunschweig 3: Dept. of Optoelectronics, University Duisburg-Essen 2:
High Performance III/V RTD and PIN Diode on a Silicon substrate, 6th Topical Workshop on Heterostructure Microelectronics TWHM Awaji Island, Hyogo, Japan, August 2005.
11.
W. PROST, I. REGOLIN, S. TOPALOGLU, J. DRIESEN, S. NEUMANN, P. VELLING, F.-J. TEGUDE
LP-MOVPE growth for high-speed HBT devices on InP a) NTT Photonics Laboratories, Atsughi, Japan, 16.08.2005, b) Sony Corporation, Semiconductor Solution Network, Atsugi 1-Tec, Japan, 18.08.2005. c) Sharp Corporation, Device Technology Laboratories, Tenri, Nara, Japan, 29.08.2005.
12.
W. PROST
Tunnelling Diodes on Silicon Substrate Seminar, Sophia University, Tokyo, Japan, 17.08.2005
13.
I. REGOLIN, V. KHORENKO, T. DO, H. WIGGERS1, F.-J. TEGUDE, W. PROST, D.SUDFELD2, J. KÄSTNER3, G. DUMPICH3, T. WEBER, E. KRUIS 1:
Inst. of Combustion and Gasdynamics, University of Duisburg-Essen, Duisburg, Germany Dept. of Experimental Physics, University Duisburg-Essen 3: Lab. of Solid-State Physics, University Duisburg-Essen 2:
Wachstum und Material-Charakterisierung von Nanowhiskern Workshop des SFB 445, Rizlern, 2005
14.
W. PROST, V. KHORENKO, A.C. MOFOR1, A. BAKIN1, E. KHORENKO, S. EHRICH, H.-H. WEHMANN1, A.SCHLACHETZKI1, F.-J. TEGUDE 1:
Inst. for Semiconductor Technology, Technical University Braunschweig
High-Speed InP-based Resonant Tunnelling Diode on Silicon Substrate 35th European Solid-State Device Research Conference ESSDERC, 12.-16.09.2005 - Grenoble, France
15.
I. REGOLIN, T. DO, S. LÜTTJOHANN1, D. SUDFELD2, V. KHORENKO, W. PROST, C. MEIER2, A. LORKE2, J.KÄSTNER2, G. DUMPICH2, F.-J. TEGUDE 1: 2:
Lab. of Solid-State Physics, University Duisburg-Essen Dept. of Experimental Physics, University Duisburg-Essen
Growth and Characterisation of Single InGaAs Nanowhiskers International Symposium on Structure and Dynamics on the Nanometer Scale, Freiburg, Duisburg, 10.13.11.2005
16.
A. POLOCZEK, I. REGOLIN, F.-J. TEGUDE, W. PROST
Wachstum und Anwendung von InGaAsP-Schichten für optoelektronische Detektoren mit gestapelten Absorptionsschichten 20. DGKK Workshop "Epitaxie von III/V-Halbleitern", 8.-9.12.2005, Duisburg
17.
I. REGOLIN, V. KHORENKO, D. SUDFELD1, F.-J. TEGUDE, W. PROST 1:
Dept. of Experimental Physics, University Duisburg-Essen
Wachstum und Charakterisierung von InGaAs Nano-Whiskern 20. DGKK Workshop "Epitaxie von III/V-Halbleitern", 8.-9.12.2005, Duisburg
Annual Report 2005 - Solid-State Electronics Department
4.6 1.
89
Publications Z.JIN, S.NEUMANN, W.PROST, F.J.TEGUDE
Passivation of InP/GaAsSb/InP double heterostructure bipolar transistors with ultra thin base layer by low-temperature deposited SiNx Solid-State Electronics, Vol. 49, No. 3, March 2005, pp. 409-412
2.
A.MATISS, J.DRIESEN, S.EHRICH,W.PROST, F.-J.TEGUDE
Bias Dependent Boolean Multivalue Logic Application of Resonant Tunneling Bipolar Transistors Proc. of 'German Microwave Conference 2005' (GMC 2005), Ulm, 05.-07.04.2005.
3.
W. PROST, P. KELLY1, A. GUTTZEIT2, V. KHORENKO, E. KHORENKO, A. MATISS, J. DRIESEN, A.MOFOR2, A.BAKIN2, S. NEUMANN, M. MC GINNITY1, A. SCHLACHETZKI2, AND F.-J. TEGUDE 1
: Intelligent Systems Engineering Laboratory, University of Ulster, Londonderry, U.K. : Inst. for Semiconductor Technology, Technical University Braunschweig
2
Design and Modelling of a III/V MOBILE-Gate with Optical Input on a Silicon substrate, Proc. of '17th Int. Conf. on InP and Related Materials' (IPRM 2005), 08.-12.May 2005, Glasgow, U.K.
4.
V. KHORENKO, I. REGOLIN, S. NEUMANN, Q. T. DO, W. PROST, AND F.-J. TEGUDE
Characterisation of GaAs nanowhiskers grown on GaAs and Si substrates, Proc. of '17th Int. Conf. on InP and Related Materials' (IPRM), 08.-12.May 2005, Glasgow, U.K.
5.
J. DRIESEN, S. TOPALOGLU, F.-J. TEGUDE
Optimizing Lateral HBT Design by Utilizing Perfomance Estimations Proc. of '17th Int. Conf. on InP and Related Materials' (IPRM), 08.-12.May 2005, Glasgow, U.K.
6.
S.TOPALOGLU, J.DRIESEN, A.POLOCZEK, F.-J.TEGUDE
Fabrication of Transferred-Substrate HBT with Simple Technology Proc. of '17th Int. Conf. on InP and Related Materials' (IPRM), 08.-12.May 2005, Glasgow, U.K.
7.
W. PROST, V. KHORENKO, A.C. MOFOR1, A. BAKIN1, E. KHORENKO, S. EHRICH, H.H.WEHMANN1, A. SCHLACHETZKI1, F.-J. TEGUDE 1
: Inst. for Semiconductor Technology, Technical University Braunschweig
High-Speed InP-based Resonant Tunnelling Diode on Silicon Substrate Proc. of '35th European Solid-State Device Research Conference' (ESSDERC), 12.-16.Sept. 2005, Grenoble, France
8.
S. KRÄMER1, S. NEUMANN, W. PROST, F.J. TEGUDE, S. MALZER1, G.H. DÖHLER1 1)
: Institute of Technical Physics, University of Erlangen,
Polarisation-sensitive switch - An integrated intensity-independent solution for 1.3 (micro)m based on the polarisation anisotropy of ordered InGaAsP Physica status solidi, Applications and materials science, Bd. 202, 2005, p. 992-996.
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9.
Annual Report 2005 - Solid-State Electronics Department
S.TOPALOGLU, J. DRIESEN, W. PROST, F.J.TEGUDE
Effect of Collector Doping on InP Based Double Heterojunction Bipolar Transistor Proc. '4th International Conference on Electrical and Electronics Engineering', 7.-11.12.2005 Bursa, TURKEY.
10.
V. KHORENKO, S. NEUMANN, I. REGOLIN, W. PROST, F.-J. TEGUDE
Photoluminescence of GaAs Nanowhiskers Grown on Si Substrate Proc. of 'Virtual Journal of Nanoscale Science & Technology', 10.01.2005
11.
T.MÜLLER1,2, A.LORKE1, Q.T.DO, F.J.TEGUDE, D.SCHUH3, W.WEGSCHEIDER3 1)
: Laboratorium für Festkörperphysik, Universität Duisburg-Essen : Robert Bosch GmbH, Stuttgart 3) : Institut für Angewandte und Experimentelle Physik, Universität Duisburg-Essen 2)
A three-terminal planar self-gating device for nanoelectronic applications Solid-State Electronics, Vol.49, pp.1990-1995, 2005
Annual Report 2005 - Solid-State Electronics Department
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Research Projects
• Quantum Tunneling Device Technology on Silicon (QUDOS) supported by European Union (EU)) together with - Max-Planck Gesellschaft zur Förderung der Wissenschaften e.V., Max-Planck-Institut fuer Festkörperforschung - Technische Universitaet Braunschweig, Institut fuer Halbleiterforschung - University of Cambridge, Department of Physics, U.K. - University of Ulster, Department of Physics, U.K. • Self-assembled building blocks for nanocomputer (ESCHER) supported by European Union (EU) together with - Department of Materials of Electrical Engineering - University College London, U.K. - University of Strathclyde, U.K. - Institute of Microelectronics, NCSR 'Demokritos' Athens, Greece • A/D converter in superconductor-semiconductor hybrid technology (Super ADC) supported by European Union (EU)) together with - Chalmers University of Technology, S - University of Twente, NL - THALES, F - Air Liquide, F - Ericcson Microelectronics, S • InP-Electronic for +80Gbit/s supported by Bundesministerium für Bildung und Forschung (BMBF) together with - Fraunhofer-Institu für Angewandte Festkörperphysik (IAF), Freiburg - Ferdinand-Braun-Institut für Höchstfrequenztechnik (FBH), Berlin • Nano Particles from the Gas Phase Sonderforschungsbereich 445 (SFB 445), supported by Deutsche Forschungsgemeinschaft (DFG) together with other departments at the University Duisburg-Essen • Key components for synchronous optical qudrature phase shift keying transmission (synQPSK) supported by European Union (EU)) together with - University of Paderborn, Germany - CeLight Israel Ltd, Israel - PHOTLINE Technologies SA, France
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Annual Report 2005 - Solid-State Electronics Department
Annual Report 2005 - Solid-State Electronics Department
4.8 Other Activities
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4.8.1
Annual Report 2005 - Solid-State Electronics Department
20. DDKK Workshop „Epitaxy of III/V-Semiconductors“
German Crystal Growers hosted by „Center of Semiconductor and Optoelectronics”
Once a year, around St. Claus but thanks to Hilde Hardtdegen from Jülich, definitely not just on St. Claus, the German III/V-growers meet. There are around 150 people; they are talking, discussing, making presentations, dispute intensively, eat, drink, enjoy themselves, ... it is like a big family event. Sometimes, they are also complaining a little bit, but in general they feel well with their subject. Indeed, mostly they are exhibiting a substantial degree of self confidence. Their subject is the epitaxial growth of III/V semiconductor crystals mainly using the metal organic vapour-phase epitaxy method. Crystal growth is represented by the German Society for Crystal Growth and Crystal Pulling (Deutsche Gesellschaft für Kristallwachstum und Kristallzüchtigung e. V.), in short “DGKK”. This Society gives the name to this family event and is its patron. The III/V crystal has stimulated many dreams. Some of them got true and a substantial number of the III/V-dreamers became Nobel laureates such as the Germans Klaus von Klitzing, Herbert Krömer, and Horst Störmer. The III/V Laser hits terabits of data via the optical fibre around the world or it just reads the movie from the DVD. But, the III/V growers want much more, of course.
Figure
InAs nanowires are growing fast and perfect on a GaAs substrate under an Au nano particle of some 10 nm diameter.
Today, nano is fascinating the scientific community, everywhere. Werner Seifert, a specialist of epitaxial nanostructures from Lund University, Sweden, explained in very detail the growth of freestanding nanowires. Under an Au seed element with a diameter down to a few nanometers, the wire grows fast with perfect crystalline structure as high resolution TEM images confirm. The group in Duisburg around Franz-Josef Tegude is working on the nanowires, too, using Au nanoparticles provided by the Sonderforschungsbereich SFB 445. Ingo Regolin stated: “We enjoy a new degree of freedom. The nanowires abandon the critical thickness limitation of lattice mismatched growth.” This way perfect InAs wire of infinite length can be grown on GaAs-substrate. Moreover, both groups in Lund and in Duisburg report on III/V luminescence on a Si-substrate stimulated by light.
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Stefan Figge, Institute of Semiconductor Physics, Bremen, reported on his work on blue Lasers. He is interested in a low threshold current and high quantum efficiency of group-III nitride Lasers for future mass production. One technological approach is edge emitting Lasers improved by a GaN substrate. The other is a surface emitting device based on AlN/Ga(In)N distributed Bragg reflectors which are now available crack-free. Group-III nitrides deserve a detailed understanding of crystal growth and hence about 50 % of the attendees are working on this subject. To produce energy out of a broad spectrum of radiation like the sun light is a further strength of III/V semiconductors. Solar cells produced in Frank Dimroth group at the Institute of Solar Energy consist of staggered absorption layers. This year they reported how tunnelling provide an ohmic I-V behaviour at a pn-junction with a high current density (> 1.2 kA/cm²). III/V solar cells are important for space applications. Here, a low weight is tremendously important. Thomas Hannappel and his group at Hahn-Meitner-Institute, Berlin, intend to grow the cells on s Silicon substrate. In Duisburg they reported on their current investigations on the arsenic stabilized surface prior to InP growth.
Figure
Peter Bursch, a famous virtuoso from Duisburg, playing the hymn on III/V-Epitaxy „There is a house in the Ruhrgebiet…”
III/V epitaxy is a lot of fun following visions and dreams, and it makes for sure hungry! Hence, the most pleasant part of meeting took place in a scenic restaurant called „Schacht 4/8“ equipped with a coal mine interior decoration. At last, Peter Bursch, a famous guitar virtuoso, played an anthem on III/V epitaxial growth based on the melody of “House of the Rising Sun“. He experienced a lot of pleased and very content faces. One of them was belonging to Michael Heuken, a former student in Duisburg, now president of the DGKK, and R&D chief of the Aixtron AG, Aachen.. A further one belongs to Ferdinand Scholz. He will host the III/V family in Ulm for 21st workshop, and he can expect a full house, again. Werner Prost
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4.8.2
Annual Report 2005 - Solid-State Electronics Department
"Electronic"-Excursion 2005 to Southern Germany and Switzerland
This year, the excursion was commonly organized by the Department for Automatic Control and Complex Systems (AKS), the Department of Electical Power Systems (EAN) and the Solid-State Electronics Department (HLT) and led about 40 students to the southern part of Germany and Switzerland. During the first visit at Siemens at Karlsruhe the group members were informed about modern automation control techniques as well as future job perspectives. From the youth hostel at Freiburg - the starting-point for all the following trips - the tour was continued to Clariant at Switzerland with a demonstration of recent fabrication techniques at a large chemical company. Power and Energy were the leading topics of the afternoon: after an interesting visit at the power network control station at Laufenburg the group members could participate in an extensive guided tour around the nuclear power plant at Beznau, Switzerland.
Fig.1
power network control station at Laufenburg a) control center b) power installations outside
During the third day, the participants of the excursion could choose between a visit at the Fraunhofer Institute for Solar Energy Systems (ISE) and the Fraunhofer Institute for Applied SolidState Physics (IAF). The last station of the third day was a visit at the winery Breisach with an impressive demonstration of the fabrication facilities but also of the diversity of excellent wines from the Breisgau area.
Annual Report 2005 - Solid-State Electronics Department
a)
b)
c) Fig. 2
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d) The winery at Breisach (Breisgau) a) modern and d) traditional wine storage b) botting plant c) "successful" wine-tasting
The excursion was closed with an alternative visit at the Daimler Chrysler motor factory at Stuttgart-Untertürkheim or at the communication research facilities at Alcatel, Stuttgart. This excursion provided for all participants a deep insight into the actual research activities from the microelectronics to the power engineering and pointed out perspectives for the future occupational decision after the study, too.
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Annual Report 2005 - Solid-State Electronics Department
Guide to the Solid-State Electronics Department (HLT)
A59
A2/A3
Abfahrt (exit) Duisburg-Kaiserberg
Autobahnkreuz Duisburg-Mitte
A40
A40
Str. (B8 Schweizer
)
Krefeld/ Moers
Hannover/ Emmerich
Wesel
Rathaus Lan d
ferm ann s
B
M
tr.
König str.
Mülheimerstr.
str.
M
L
LT
Highway
main entrance (Haupteingang)
tr. ts ar oz
Düssel
dorfer
Str. (B 8)
e Düss
St er
er ldorf
Str.
nb us ch we g
(B 8)
mm Ko
r. st
Loth ars tr.
er str .
.
Lotharstr .
St er nb us ch we g
(B 8)
ck str Bis ma r
nie lo Ko
andantenstr.
Bü rg er str
Ka mm
ZHO *)
Fin ken str.
.
Neudorfer Str.
Düsse ldor
Hbf
Lotha rstr
,
fer Str.
er Mülheim
Zoo
A59 Abfahrt (exit) Duisburg-Wedau
Düsseldorf Sportpark Wedau
N
Köln
A3
*) ZHO: Zentrum für Halbleitertechnik und Optoelektronik (Center for solid-state electronics and optoelectronics) Travel by car: The Solid-State Electronics Department (HLT) at the ZHO (Zentrum fuer Halbleitertechnik und Optoelektronik) can be reached by car via various highways: A3 from the South, A40 from the Netherlands and the East, A2/A3 from the North. Exit: Duisburg-Kaiserberg or Duisburg-Wedau (see map). Travel by train: The main station (Hauptbahnhof (Hbf)) is 25 min (walk) away from the Solid-State Electronics Department (HLT) and the ZHO (see map). Take the bus 933, 936 or 924 to "Universität/Städtische Kliniken" and leave it at "Universität (Uni-Nord)" or take the tram 901 to "Mülheim" and leave it at "Universität". Travel by plane: After landing at Duesseldorf Airport (the next airport to Duisburg) take the city-train (S-Bahn) S1 from Duesseldorf to Duisburg main station (Hauptbahnhof (Hbf)). For further informations see: "Travel by train":
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