Agilent Technologies FPGA Dynamic Probe for Mixed-Signal Oscilloscopes N5397A for Infiniium 54830 Series MSOs N5406A for 6000 Series MSOs Data Sheet

Debug and validate your FPGA designs faster and more effectively Until now, designers of FPGA-based systems often relied on a time-consuming manual process to make internal FPGA measurements. Collaborative development between Agilent Technologies and Xilinx has produced a faster and more effective way to debug and validate Xilinx FPGAs and the surrounding system using an Infiniium 54830 Series mixed-signal oscilloscope (MSO) or 6000 Series MSO. The industry-first Agilent FPGA dynamic probe, used in conjunction with an Agilent MSO can save design teams hundreds of hours per Xilinx FPGA design.

Traditional FPGA debug and validation Signals that were previously readily available on the PC board in embedded designs now may exist exclusively as nodes within the FPGA , which makes in-circuit debug and validation difficult. A typical approach is to take

advantage of the programmability of the FPGA to route internal nodes to a small number of physical pins that a mixed-signal oscilloscope (MSO) can measure. While this approach is useful, it has significant limitations: • Since pins on the FPGA are typically an expensive resource, there are a relatively small number available for debug. Because one pin is required for each internal signal to be probed, internal visibility is limited. • When different internal signals need to be accessed, you have to change the FPGA design to route these new signals to pins. This process requires time-consuming design recompiles, and it affects the timing of the FPGA design. • When you view internal signals on an MSO, keeping track of them manually can be difficult. When the design is changed and new internal signals are routed out, you need to manually track them, creating a potential source of confusion and errors.

A better way to debug and validate an FPGA design

Now there is a better way to debug and validate your FPGA designs. The N5397A for Infiniium 54830 Series MSOs or N5406A for the 6000 Series MSOs FPGA dynamic probe increases your visibility into your design and speeds and simplifies the debug process. The N5397A and N5406A support Xilinx’s newest FPGA product families including the Virtex-4, Virtex-II Pro, VirtexII, and Spartan-3 series that cover

the gamut of price and performance. Industry-leading capabilities built into the Agilent N5397A and N5406A include: • Increased visibility — The FPGA dynamic probe lets you measure up to 64 internal FPGA signals for each debug pin. With the Infiniium 54830 Series’ or

Probe outputs on FPGA pins

the 6000 Series’ 16 digital timing channels connected to these debug pins, you can access up to 1024 internal signals within a single design. Taking advantage of the power of the MSO, you can correlate these internal FPGA signals with external analog content to help track down difficult signal integrity problems in your embedded system.

SW application installed on and licensed to an Infiniium 54830 Series MSO

PC board FPGA ATC2

Insert ATC2 core with Xilinx Core Inserter

Parallel Port Xilinx cable JTAG

Figure 1. Block diagram of the FPGA dynamic probe software running on and licensed to an Infiniium 54830 Series MSO. The software controls via JTAG the set of internal FPGA signals you want to measure though the Agilent Trace Core-2 (ATC2) inserted inside the FPGA.

Probe outputs on FPGA pins

SW application can be licensed to a particular PC or particular MSO

SW application installed on a PC remotely connected to 6000 or Infiniium MSOs

PC board USB LAN GPIB

FPGA ATC2

Insert ATC2 core with Xilinx Core Inserter

Parallel Port Xilinx cable JTAG

Figure 2. Block diagram of the FPGA dynamic probe software running on a PC remotely connected to 6000 or Infiniium MSOs. The software application can be licensed to a particular PC to remotely connect to multiple remote MSOs, licensed to a particular MSO that can be remotely connected to multiple remote PCs. The software controls via JTAG the set of internal FPGA signals you want to measure and remotely controls the MSO via USB, LAN, or GPIB.

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A better way to debug and validate an FPGA design

• Faster probing changes — The FPGA dynamic probe enables you to move internal FPGA probe points in less than a second, making it fast and easy to measure different sets of internal signals without recompiling or changing your design. Since no design changes are taking place, FPGA timing stays constant when you select new sets of internal signals.

• Automatic setup of the MSO — The FPGA dynamic probe automatically turns on the appropriate digital channels or buses to align with the set of internal signals you select. In addition, the tool automatically maps internal signal names from the FPGA design tool to the MSO channel labels. This eliminates unintentional mistakes and saves hours of time compared to manually completing this task.

4-16

4-16

Selection MUX

4-16

4-16

To FPGA pins

Select

4-16

Change signal bank selection via JTAG

JTAG

Figure 3. With the Agilent Trace Core-2 (ATC2) inserted into your FPGA, access up to 64 internal FPGA signals on each debug pin that are connected to the MSO’s digital timing channels. You decide how many pins to devote to debug, but when utilizing all of the MSO’s 16 digital timing channels, it means you can access up to 64 x 16 = 1024 internal FPGA signals in a single design.

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A quick tour of the dynamic probe solution

Design step 1: Create the Agilent Trace Core-2 (ATC2) Use the Xilinx Core Inserter software to select your ATC2 parameters and to create a debug core that best matches your development needs. Parameters include number of pins, number of signal banks and capture mode (state or timing). The Agilent MSOs’ 16 digital channels are timing acquisition only to capture both state and timing core signals. Infiniium MSOs do support a pseudo state bus display capability using post-acquisition processing on its bus groupings and an acquired clock signal to intuitively view state core signals. 6000 MSOs do not have a pseudo state bus display capability.

Figure 4. Create an Agilent Trace Core-2 (ATC2) with Xilinx Core Inserter software.

Design step 2: Select groups of signals to probe For each signal bank, use the Xilinx Core Inserter software to specify groups of internal FPGA signals you want visibility to.

Figure 5. Select groups of signals to probe with Xilinx Core Inserter software.

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A quick tour of the dynamic probe solution

Measurement step 1: Initiate the FPGA dynamic probe The FPGA dynamic probe application software can either be run inside a Windows-based Infiniium MSO, or on a PC remotely connected via LAN, USB, or GPIB to either a 6000 MSO or Infiniium MSO. With a Xilinx cable connected between the parallel port of the Infiniium MSO or PC where the application is running and the device under test’s JTAG scan chain, you are ready to control the Agilent Trace Core-2 and begin accessing internal FPGA signals.

Figure 6. Menu selection when the FPGA dynamic probe application is run inside a Windows-based Infiniium MSO.

Figure 7. Choose the Run MSO FPGA Dynamic Probe application from the Windows Start menu when the FPGA dynamic probe application is installed on a PC.

Figure 8. With the FPGA dynamic probe application running on a PC remotely connected to an MSO, this instrument connection setup screen shows the PC-locked or Oscilloscope-locked licenses that were found. Also provided is the field to enter the remote MSO instrument address that the user wants to connect to via LAN, USB, or GPIB.

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A quick tour of the dynamic probe solution

Measurement step 2: Establish a connection between the MSO and the ATC2 The FPGA dynamic probe application establishes a connection between the Infiniium MSO or PC and any devices that are on the JTAG scan chain. If there are multiple FPGA devices with an ATC2 on the JTAG scan chain, the software allows you to select the one with which to communicate. You can define your own core and device names.

Figure 9. FPGA dynamic probe device connection setup screen.

Measurement step 3: Map FPGA debug pins Graphically specify how the FPGA debug pins (the signal outputs of the ATC2) are connected to the logic probe that is being used on the MSO’s logic connector. Select the Agilent logic probe from the available list and simply drag and drop the FPGA debug pins to the logic probe channels as you have them routed on the PC board.

Figure 10. Graphical pin mapping of FPGA debug pins.

You can skip the graphical mapping of FPGA debug pins. For ATC2 cores with auto setup enabled, each pin of the ATC2 core, one at a time, produces a unique stimulus pattern. The instrument looks for this unique pattern on any of its acquisition channels. When the instrument finds the pattern, it associates that instrument channel with the ATC2 output pin producing it. It then repeats the process for each of the remaining output pins eliminating the need to graphically enter probe layout information. 6

Figure 11. Auto pin mapping of FPGA debug pins for ATC2 cores with auto setup enabled.

A quick tour of the dynamic probe solution

Measurement step 4: Import signal names In seconds, the FPGA dynamic probe application reads a *.cdc file produced by the Xilinx Core Inserter software. The names of the signals you defined while designing your FPGA that are accessible by the FPGA dynamic probe are automatically mapped to the MSO’s digital channel labels. With this capability, you can easily identify which internal signals are currently being viewed among the hundreds of internal signals that are accessible.

Figure 12. Automatically import signal names you defined while designing your FPGA to the MSO’s digital channel labels.

Measurement setup complete: Make measurements Quickly change which signal bank is routed to the MSO’s digital channels. A single mouse click tells the ATC2 to switch to the newly specified signal bank without any impact to the timing of your design. To make measurements throughout your FPGA, change signal banks as often as you need. User-definable signal bank names make it easy to identify and select the part of your design you wish to measure. Figure 13. With the measurement setup complete, easily switch to new signal banks within a second.

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A quick tour of the dynamic probe solution

Correlate internal FPGA activity with external analog content With each new signal bank selection, the FPGA dynamic probe application turns on the appropriate digital channels and automatically displays the appropriate signal names on the digital channels. But the visibility into your design doesn’t stop there. The MSO tightly integrates analog channels with these digital channels, so you can easily correlate analog content outside the FPGA with digital signal activity inside the FPGA. Now you can quickly track down signal integrity problems throughout the embedded system and uncover cause-and-affect relationships between internal and external FPGA signals.

Figure 14. Infiniium MSO screen (top) and 6000 MSO screen (bottom), capturing internal FPGA signals on digital channels, correlated to analog signals external to the FPGA.

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Solution characteristics

Maximum insight Using the FPGA dynamic probe application, each FPGA debug pin provides access to up to 64 internal signals. The number of debug pins can range from 4 to 16 depending on your needs. When using a synchronous state capture core, you can use the Infiniium MSO’s pseudo state bus display capability that employs post-acquisition processing on its bus groupings. This capability requires one additional FPGA debug pin for the state clock input source. Note that the Infiniium MSO does not use the standard state clock input connector on a logic probe. Therefore, this state clock signal needs to be routed to one of the 16 digital data channels of the logic probe. Note that the 6000 MSO does not provide this pseudo state bus display capability.

Number of debug pins

Maximum internal signals

4

256

5

320

6

384

7

448

8

512

9

576

10

640

11

704

12

768

13

832

14

896

15

960

16

1024

FPGA dynamic probe for MSOs comparison Attribute

Infiniium MSO

6000 MSO

FPGA dynamic probe product

N5497A

N5406A

Number of logic timing channels

16

16

Logic channel sample rate

1 GSa/s

1 GSa/s - 2 GSa/s

Logic channel memory depth

32 Mpts standard

500 kpts - 1 Mpts standard 4 Mpts - 8 Mpts optional

Bus display with numerical readout

Yes

No

Pseudo state bus display

Yes

No

Max character length for channel labels

16

6

FPGA dynamic probe application can be installed and run inside MSO

Yes

No

FPGA dynamic probe application can be installed and run on a PC remotely connected to MSO

Yes

Yes

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Solution characteristics

Supported hardware Agilent mixed-signal oscilloscopes (MSO)

N5397A: Infiniium 54830D, 54831D, 54832D, 54833D N5406A: MSO6032A, MSO6034A, MSO6052A, MSO6054A, MSO6102A, MSO6104A

Agilent logic probes

40-pin pod connector versions of Soft Touch, Mictor, Samtec, and flying lead; Infiniium MSO comes standard with a 40-pin female logic cable; N5406A provides a 40-pin female cable for the 6000 MSO

Minimum PC requirements for running the FPGA dynamic probe application

Pentium III 800 MHz, 256 MB RAM or better running Windows 2000 or Windows XP Pro

Xilinx FPGA families

Virtex-4, Virtex-II Pro, Virtex-II, Spartan-3

Xilinx JTAG cables

Parallel 3 and 4

Xilinx FPGA families

Virtex-4, Virtex-II Pro, Virtex-II, Spartan-3

FPGA dynamic probe application characteristics Maximum number of devices on a JTAG scan chain

256

Maximum number of Agilent Trace Cores supported per FPGA device

1

Agilent Trace Core-2 characteristics Number of output signals

User definable: 4 to 16 signals in increments of 1 signal

Signal banks

User definable: 1, 2, 4, 8, 16, 32, or 64

Modes

Timing (asynchronous) mode or state (synchronous) mode; MSOs provide timing acquisition only to capture both timing and state core signals; Infiniium MSO’s pseudo state bus display capability can be used to intuitively view state core signals

FPGA resource consumption

Approximately 1 slice required per input signal to ATC2. Consumes no BUFGs, DCMs, or Block RAM resources. See resource calculator at www.agilent.com/find/MSOfpga

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Solution characteristics

Compatible design tools ChipScope Pro* version

FPGA dynamic probe app. version

Infiniium 54830 Series MSO SW version

6000 Series MSO SW version

Primary new features added

6.2i, 6.3i

1.00 or higher

4.00 or higher

1.30 or higher

N/A

7.1i

2.00 or higher

4.20 or higher

1.30 or higher

Plug & run (auto pin mapping), ATC2 “always on” option, ATC2 max banks increased from 32 to 64

* Xilinx ChipScope Pro is required and includes Xilinx Core Inserter and Core Generator

Synthesis

Xilinx Core Inserter produces an ATC2 post-synthesis (pre-place and route) making the cores synthesis independent. ATC2 produced by Core Generator are compatible with: • Exemplar Leonardo Spectrum • Synopsys Design Compiler • Synopsys Design Compiler II • Synopsys FPGA Express • Synplicity Synplify • Xilinx XST

Additional information is available at www.agilent.com/find/MSOfpga.

Oscilloscope compatibility

See compatibility table above for required Agilent MSO software version. You can upgrade existing Infiniium 54830 Series MSOs with earlier software revisions using free upgrade software available for order on CD from www.agilent.com/find/ infiniium_software and downloadable from www.agilent.com/find/ infiniium_sw_download.

For existing Infiniium 54830 Series MSOs with software version A.02.xx (Windows 98) or lower, order the N5383A Infiniium Performance Upgrade Kit to obtain version A.03.xx (Windows XP Pro) or higher.

You can upgrade existing 6000 Series MSOs with earlier software revisions using free upgrade software downloadable from www.agilent.com/find/ 6000-software.

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Ordering Information

The FPGA dynamic probe software uses perpetual node-locked licenses (not floating or counted licenses). You can install the FPGA dynamic probe application on any PC (Windows 2000 or Windows XP Pro) or Windows-based Infiniium 54830 Series MSO. However, the license type determines how the application can be used with Infiniium MSOs or 6000 MSOs. Two types of licenses are available: • Oscilloscope-locked license — This enables the FPGA dynamic probe application, installed on any PC or inside an Infiniium 54830 Series MSO, to connect to and use a single licensed MSO. This type of license permits multiple users with multiple PCs to share a single MSO in a lab.

To purchase the FPGA dynamic probe for a new or existing Infiniium 54830 Series MSO, please order as follows: Model Number

Description

N5397A-001

FPGA dynamic probe for Infiniium MSOs, Oscilloscope-locked license

N5397A-002

FPGA dynamic probe for Infiniium MSOs, PC-locked license

To purchase the FPGA dynamic probe for a new or existing 6000 Series MSO, please order as follows: Model Number

Description

N5406A-001

FPGA dynamic probe for 6000 MSOs, Oscilloscope-locked license. Includes a 40-pin female-female logic cable for connecting the 6000 MSO’s 16 digital channels to Agilent logic probes.

N5406A-002

FPGA dynamic probe for 6000 MSOs, PC-locked license. Includes a 40-pin female-female logic cable for connecting the 6000 MSO’s 16 digital channels to Agilent logic probes.

• PC-locked license — This enables the FPGA dynamic probe application, installed and licensed on a single PC, to connect to and use any Agilent MSO covered by the license. This type of license permits a single user on a single PC to access multiple different MSOs the user may have in a lab.

Related Literature Publication Title

Publication Type

Publication Number

Infiniium 54830 Series Oscilloscopes

Data Sheet

5988-3788EN/ENUS

6000 Series Oscilloscopes

Data Sheet

5989-2000EN/ENUS

Planning Your Design for Debug: FPGA Dynamic Probe

Data Sheet

5989-1593EN

Windows® is a U.S. registered trademark of Microsoft Corporation. 12

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