Advantages of SONOS memory for embedded flash technology Krishnaswamy Ramkumar and Bo Jin, Cypress Semiconductor - September 29, 2011

The demand for embedded non-volatile memory (eNVM) in system-on-chip (SOC) designs has grown exponentially in recent years as newer applications evolve in communications and consumer electronics. The memory content of complex SOCs has increased due to more sophisticated firmware and software demand on rich application features. Embedded flash (eFlash) memory is highly desirable in most applications to store critical data and code due to its robust endurance. In addition, eFlash enables field programming that provides great flexibility for last minute system level changes. eFlash technology usually tracks behind the baseline logic technology ramp-up by about three years and mainly aims for second wave applications; therefore, in addition to real flash reliability, an ideal eFlash technology should have the following features: ● ●

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Simple integration into Logic baseline process leads to fewer masks, low manufacturing cost No change to baseline Si models, which means existing design IPs are preserved  re-use IP, time to market Compatible with existing transistors High intrinsic yield and easy to test Allows both Flash and EEPROM on the same chip

Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory technology has all the above features and is ideally suited for eFlash. SONOS or Charge Trap Memory Technology A SONOS memory device uses an insulating layer, such as silicon nitride, with traps as the charge storage layer. The traps in the nitride capture the carriers injected from the channel of a MOS transistor and retain the charge. This type of memory is also known as charge trap memory. Since the charge storage layer is an insulator, this storage mechanism is inherently less sensitive to pinhole defects, and it is more robust in terms of yield and data retention. SONOS memories have very few “weak” bits, and this makes testing simpler. Another key advantage of SONOS technology is the relatively low voltages required for program/erase as compared to Floating gate memory. The 65-nm SONOS technology demonstrated is based on F-N tunneling for both program and erase, which dramatically improves the endurance, compared to using hot electron injection (HEI) for programming. 65nm SONOS technology integrates a highly reliable SONOS transistor into the existing 65nm CMOS process flow with only three additional masking layers. It has a low thermal budget, which has minimal impact on the electrical parameters of the existing CMOS FETs. The SONOS transistor shares many of the key process steps with the CMOS transistors. Therefore, many regions of the SONOS transistor, such as source, drain, and gate, are identical to those of the CMOS transistors.

This makes the process architecture of the embedded SONOS technology simple. The 65nm SONOS technology uses low program and erase voltages. Hence the flash macro utilizes existing core and I/O gate oxides and no additional high voltage gate oxide is required.

Fig.1: Schematic (top) and TEM cross section (bottom) of SONOS FET A transmission-electron-microscopy (TEM) cross section of an actual SONOS transistor integrated into 65 nm baseline process is shown in Figure 1.The schematic is a SONOS transistor that is fabricated using a typical foundry logic CMOS process flow. The device has salicided gate, source, and drain regions and the gate stack is made up of salicided polysilicon. The embedded SONOS technology typically offers multiple cell options to fit into different application, without compromising reliability. The program speed is 1 to 5 ms and erase speed is 5 to10 ms depending on application options and macro architecture. The same cell can be used for Flash and EEPROM. SONOS Cell Reliability A key requirement for an NVM cell is reliability. The end-of-life (EOL) threshold voltage (Vt) window of a NVM cell is determined by the degradation caused by program/erase cycles (endurance) and Vt decay during storage (data retention). Endurance is typically characterized by cycling a SONOS cell through the required number of program/erase cycles and measuring the shift of program and erase Vts. Retention is characterized by taking the SONOS cell through a fixed number of program/erase cycles and then measuring the change of Vt (program or erase) with time at an elevated temperature. Figure 2 illustrates the typical endurance and retention characteristics.

Fig 2. Endurance (top) and Retention Characteristics (bottom) of 65 nm SONOS FET The endurance characteristics show that Vt shift is negligible after 10,000 program/erase cycles at 70°C. The retention characteristic shows that the EOL Vt window is significantly larger than the minimum window required for sensing the state of a NVM cell. SONOS Integration into foundry 65 nm process The integration scheme includes a dual-gate-oxide process, which enables the chip to be compatible with multiple supply voltages. Cypress recently was successful in integrating the embedded SONOS flash technology into UMC’s LL65 baseline process, and achieved working silicon on a 576KB flash macro test chip (Fig. 3). The key features of this macro are given in Table-1. The macro exhibits excellent retention at 150 C after 10,000 cycles (Fig.4)

Fig.3: SONOS eFlash Test Chip and its specifications (Table 1)

Fig.4: Retention characteristics of Flash Macro The optimized thermal budget of SONOS integration ensures a negligible impact on the electrical parameters of existing CMOS devices. This means that with minimal changes, all the design IP of the original CMOS platform can be used in the embedded ICs. The SONOS process has shown no impact to 65-nm baseline design IP as well as device matching in high-volume production. Further, it has been shown that there is no impact to the baseline yield due to the integration of SONOS. The table below shows MOSFET parameter matching between embedded SONOS and pure CMOS baseline processes on key device parameters (P1= Priority 1 parameters; P2= Priority 2 parameters).

The yield wafer maps on a SRAM product with the key SONOS process incorporated is compared with the baseline yield in the figure below. It shows negligible impact of the SONOS process on the baseline yield.

Figure 5: SONOS Split #1 (left); SONOS Split #2 (center); Baseline CMOS (right)

The SONOS cell used in this macro can be adopted for an EEPROM also with minor changes in program / erase conditions. This enables easy integration of flash and EEPROM arrays on the same die. Summary SONOS technology is a low cost, highly reliable approach to embed nonvolatile memory into logic platforms. The CMOS design IP is virtually unchanged by SONOS integration. This technology has excellent endurance and data retention and is scalable to more advanced technology nodes with very little change in process integration. Cypress has successfully integrated its proprietary SONOS into the CMOS baseline at UMC and demonstrated a functional flash macro. About the Authors Krishnaswamy Ramkumar, Senior Member of Technical Staff Krishnaswamy Ramkumar has been involved in research and development of advanced semiconductor technologies at Cypress Semiconductor since 1993. He has contributed in technology nodes ranging from 0.50 µm to 65 nm during this period. His work has been mainly in the front end processes such as Shallow trench Isolation, gate oxidation and ONO formation. He has 55 issued US patents to his credit. Ramkumar received his MS and PhD degrees from Indian Institute of Science, Bangalore. Prior to joining Cypress he was a faculty member at Indian Institute of Science and a Visiting Research Associate at Rensselaer Polytechnic Institute, Troy, NY. Bo Jin, Managing Director Bo Jin directs Cypress's IP business unit as general manager, as well as develops strategic business relationships in Asia Operations. Prior to his current position, Bo Jin served as Director of Foundry of Cypress's Corporate Operation. Bo built his career in many aspects, including roles as product manager, design program manager, and multiple positions in technology R&D during his early years in Cypress. Bo started his job as night shift fab manufacturing sustaining engineer. Bo Jin received his B.S. degree in Material Science and B.A. degree in Economics & Business Management from Shanghai Jiao Tong University in 1992. He got his MS in material science from Arizona State University. He completed the Harvard Business School Executive MBA Program in 2007. He has 15 US patents. Bo served as the Chairman and president of North America Chinese Semiconductor Association (NACSA), a non-profit organization bridging Silicon Valley and China, with more than 4000 professional members.