Advances in flash memory devices *

Materials Science-Poland, Vol. 28, No. 1, 2010 Advances in flash memory devices* C. LUDWIG1**, M.F. BEUG2, K.-H. KÜSTERS3 1 Q-Cells SE, OT Thalheim,...
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Materials Science-Poland, Vol. 28, No. 1, 2010

Advances in flash memory devices* C. LUDWIG1**, M.F. BEUG2, K.-H. KÜSTERS3 1

Q-Cells SE, OT Thalheim, Sonnenallee 17–21, 06766 Bitterfeld-Wolfen, Germany

2

Physikalisch-Technische Bundesanstalt (PTB), Bundesallee 100, 38116 Braunschweig, Germany 3

Conergy SolarModule GmbH, Conergy-Straße 8, 15236 Frankfurt (Oder), Germany

Fundamental challenges are discussed concerning the down-scaling of flash memory cells for mass storage applications. A general scaling issue for all various memory cell concepts is the structuring limit of conventional lithography. Therefore sub-lithographical structuring methods like e.g., double-patterning for future flash chips, have been evaluated. Another common scaling challenge of charge trapping (CT) and floating gate (FG) cells, the two future concurrent flash memory cell concepts, is the introduction of new materials such as high k dielectrics. Their implementation into CT and FG cells and the scaling related electrical issues of both cell concepts is also been discussed. Keywords: non-volatile memory; flash; charge trapping; SONOS; TANOS; high workfunction gate; high-k dielectric; double patterning; erase saturation

1. Introduction Flash memories enjoy a strongly growing demand. Further productivity improvements in the manufacture of flash devices have been achieved by continued scaling, recently formulated as Hwang’s law [1]. Currently, the smallest flash products are available in the 50 nm generation. Attempts to increase the density of bits per area have addressed the challenges of designing as well as fabrication of the flash cell.

2. Lithography challenges for future flash technology nodes Silicon structuring is currently facing a paradigm change. Considerable effort has been spent on techniques to enhance the resolution of the illumination systems, opti_________ *

The paper has been presented at the 3rd Workshop on Hybrid Nanostructured Materials, Prague, 5 November 2007. ** Corresponding author, e-mail: [email protected]

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mizing the usage of the 193 nm wavelength. The most prominent one is the successful development of immersion scanners, allowing numerical apertures larger than 1. In order to achieve smaller features, a next step could be the introduction of extreme UV (EUV) scanners, operating at the wavelength of 13.5 nm. However, this spectral range comes along with a number of challenges as e.g. new diffraction elements, new mask materials and mask manufacturing, new resistance materials, and others. As an alternative, more conservative approach, so called double patterning techniques have been developed recently. These methods consist of process sequences which generate smaller pitches than the ones which are feasible by direct application of lithography tools. Basically, there are two options: one is subsequent printing of even and odd lines of an array separately, i.e. simply applying two subsequent lithography steps with an appropriate displacement. The other option uses spacers along the lines of a single lithography, and thus makes a pair of lines per one lithographically generated line. Figure 1 illustrates a possible process flow. In Figure 2, we show a part of a flash array including the fan out, resulting from this technique.

Fig. 1. Schematic process flow for double patterning: lithography defines an array with only half the number of lines, reflecting twice the desired pitch (a). The lines are narrowed by a trim etch (b) and a spacer is placed along the lines (c). The room between the lines is filled by the same material as the lithographically defined lines (d). After removing the spacers (e), a line array is obtained in the desired pitch (f)

Fig. 2. Wordline fanout of a 36 nm half pitch array

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This technique opens a new path to the next flash shrink generations without the need of expensive investment in lithography tools [2].

3. NAND shrink path The highest bit densities have been continuously achieved in standard floating-gate (FG) NAND flash products, utilizing Fowler–Nordheim (FN) tunnelling for write and erase operations. However, there remain several challenges associated with persistently minimizing the dimensions of conventional floating gates (FG) in flash devices [3]. One of them is the crosstalk between adjacent FG cells [4], caused by the electrostatic interaction of the stored charge of all neighbouring floating gates on the FG and on the channel region of one particular flash cell. There is a significant capacitive coupling between neighbouring flash cells due to the relatively large height of FG poly silicon storage elements. Their height is typically in the order of twice the halfpitch, which is the distance between adjacent cells or even larger. As a result of this cross-talk, the unit elements of a Gbit scale flash memory array can no longer be considered independent. Luckily, the coupling between adjacent FG is a deterministic effect. It can be treated by appropriate programming algorithms which extrapolate the cross-talk from the data pattern and adjust the amount of injected electrons for the individual flash cells accordingly. Another challenge to be discussed here is related to the high wordline voltages needed for programming. During programming, selected and unselected wordlines may happen to be direct neighbours. Their difference in voltage becomes a challenge as soon as it reaches the level of the breakdown field strength of the insulating dielectric between them. A brief glance at numerous sub-50 nm flash devices shows that this is becoming a significant issue. The magnitude of the program pulse voltages is determined by two factors: the tunnelling oxide (TOX) thickness and the efficiency of the capacitive voltage transfer from the wordline to the FG body, called the gate coupling ratio [5, 6]. The latter depends on FG cell geometry and dielectric constants of the insulating materials around the FG. The TOX thickness dictates the voltage difference across the TOX barrier in order to achieve FN tunnelling. The data retention requirement of 10 years leads to a typical TOX thickness between 8 and 9 nm, resulting in a voltage difference of 10–13 V between FG and the channel region. With typical values of the gate coupling ratio of 0.5~0.6, wordline voltages typically exceed 20 V. Provided the voltage of an unselected wordline is kept at a half or a third of this value, the dielectric breakdown between selected and unselected wordlines during programming becomes an issue for technology generations below 30 nm. Therefore, the reduction of the programming voltage and the reduction of the FG–FG coupling deserve utmost attention. Suggestions have been made to reduce the programming voltage by modifying the TOX barrier. Instead of a single SiO2 layer, a tailored bandgap-engineered tunnelling

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barrier can effectively enhance the tunnelling probability at high fields during programming, and still serve as a sufficient tunnelling barrier at low fields, keeping the escape rate low enough for good data retention [7–9]. Whatever material is investigated for this type of bandgap-engineering, it eventually must reach the high and mature quality of SiO2 with respect to defect level and breakdown voltage. Another possibility for a reduction of programming voltage is an increased capacitive coupling between control gate and floating gate. This can be achieved by inserting a high k material as interpoly dielectric (IPD) between the control gate and floating gate instead of the conventional oxide–nitride–oxide arrangement. Again, high electric breakdown fields and low trap density are important parameters. In addition, a large bandgap is desirable to act as an effective tunnelling barrier. Viable candidate materials are e.g. Al2O3 or HfSiO. Figure 3 shows an example of a 48 nm half pitch FG flash with Al2O3 IPD. Here, the programming voltage is reduced by 2 V.

Fig. 3. TEM cross-section of a 48 nm half pitch floating gate flash. Interpoly dielectric between the floating gate and control gate consists of a bilayer of 5 nm oxide and 7 nm Al2O3

Fig. 4. 48 nm NAND flash with Ti(Si)N metal gate

Another very critical issue in FG flash cells beyond the 40 nm technology generation is the placement of the control gate (CG) plug between the cells [10]. This plug is important for the following two reasons. On the one hand, this increases the capacitive coupling area between CG and FG which allows gate coupling ratios in the range mentioned above. On the other hand, this CG plug electrically shields and therefore reduces the charge crosstalk in wordline direction between adjacent floating gates. But below 40 nm half pitch, there is literally not enough space between the flash cells for the CG plug. With a typical interpoly thickness of 12~15 nm, which has to fit twice into the intercell spacing, not much room is left to insert the CG poly as well. Furthermore, a conventional poly CG will always experience a depletion layer of a few

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nm thickness once operating voltages are applied. Therefore a metallic conductor seems desirable. Figure 4 demonstrates such an example with Ti(Si)N as a CG electrode.

4. Charge trapping flash An elegant way to address all the mentioned concerns in NAND flash is the replacement of the FG poly by a thin charge trapping layer, i.e. a SONOS-type (silicon –oxide–nitride–oxide–silicon) flash cell with proper material selections (see also Fig. 5). Both the programming voltage reduction and the coupling between adjacent flash cells can be significantly reduced in such a kind of charge trapping flash.

Fig. 5. Material options to improve the properties of a charge trapping flash

Here, the storage layer has a typical thickness in the order of 10 nm or below, much less than a typical FG poly. Therefore, the mere geometry of this stack provides a much smaller coupling area to accommodate an adjacent storage cell, thus minimizing the lateral cross-talk. We have used our Twinflash technology (see below) to quantify the cross-talk between charge trapping cells. Twinflash cells in the buried bit line (BBL) array configuration [16] are planar cells without shallow trench isolation (STI) between adjacent cells (or wordlines). Figure 6 shows the cross-talk analysis on a charge trapping cell with a 6 nm thick Si3N4 layer. As the worst case, the two neighbours of an erased flash cell (low Vt) are considered programmed (high Vt). The two neighbour cells are supposed to sit on the same bit line as the erased flash cell. Measured data and simulations show that for an extremely aggressive 20 nm spacing between the adjacent cells, the cross talk creates a Vt shift of 400~500 mV, whereas only a 100 mV cross-talk is observed for a 63 nm spacing. This result is generally also valid for the most commonly used NAND architecture. It shows that cross-talk between neighbouring CT cells cannot be neglected, as sometimes stated in the literature. The programming voltage in charge trapping (CT) flash cells is generally reduced by the thinner tunnel oxide compared with FG cells (5 nm instead of 8 nm) and the overall smaller electrical thickness of the whole CT dielectric stack. A high k dielectric material as the top-oxide is introduced to solve the SONOS erase saturation issue [11] when tunnel oxides thicker than 4 nm are used.

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Fig. 6. Crosstalk in Twinflash 63 nm: simulation and measurement. Upperpart shows a sketch of the cross section perpendicular to the channel with simulated electron distributions in the channel. The gates are represented by white areas, with their respective voltages. The black lines are the simulated equipotential lines. The channel region of the central gate is in inversion. Obviously, the effective channel width strongly depends on the gate voltages of the left and the right gate. Lower part shows the simulated threshold voltage shifts in function of the gate potential on the neighbour cells and the measured shift of a 63 nm Twinflash cell array

The erase saturation is a fundamental challenge of the conventional silicon based SONOS flash with symmetrical materials and geometry. In such a standard structure, it turns out that the Vt after erasure cannot go much below the virgin value. The erase

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voltage is supposed to create a hole tunnelling current from the substrate through the bottom oxide into the storage nitride. But as soon as the majority of stored electrons is neutralized, electrons out of the gate will start penetrating through the top oxide into the storage nitride and will eventually compensate the hole injection, as indicated in Fig. 7. Using a high k dielectric as a top oxide will improve the erase saturation issue compared to a SiO2 top oxide, due to its lower internal field. Al2O3 is the preferred candidate because it acts as an effective tunnelling barrier due to its high bandgap and its relatively low trapping state density.

Fig. 7. Erase saturation

Fig. 8. Erase efficiency for charge trapping flash: a) with Al2O3 as high k top oxide, b) with Al2O3 as high k top oxide and in addition TaN as a gate electrode. Sample (b) with the high work function metal gate reaches significantly lower erase Vt. See also K.H.Küsters et al., MSE2008

The most recent developments of charge trapping flash, however, utilize a gate material with a large work function in addition to high k top oxide dielectric. Typical materials are TaN, TiN, W, WN [10, 12]. The reason for the need of a high work func-

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tion gate is the problem of the erase saturation. If the band offsets of the high k top oxide and the work function of the gate material are large enough, tunnelling across the high k top oxide will be strongly suppressed, thus eliminating the erase saturation. Figure 8 demonstrates the improvement in erase level for a TANOS charge trapping flash (TaN gate–Al2O3 top oxide–Si3N4 charge storage–SiO2 bottom oxide–Si channel) in comparison with a SANOS stack (with standard n+ gate instead of the TaN gate). However, in the TANOS flash, the erase performance and the data retention seem to be two conflicting target parameters. The introduction of Al2O3 top oxide turns out to degrade the data retention. This effect can be ascribed to the somewhat lower bandgap compared with SiO2 and to some detrapping inside the Al2O3.

5. Localized charge trapping flash The usage of trap centres in a dielectric for storing the charge provides an additional advantage over a poly FG flash. Electrically confined local storage of more than one bit per flash cell is feasible if localized charge injection mechanisms are used. Hot electron (CHE) and hot hole injection into a trapping layer like Si3N4 are candidates for the write and erase mechanisms, as implemented in NROMTM [13], TwinflashTM [14–16], MirrorbitTM [17] and other products. A typical process sequence consists of standard ONO deposition as trapping layer, buried bit lines, a standard gate, standard contact and standard metallization.

Fig. 9. Cross-section of a Twinflash 63 nm cell, along and perpendicular to the wordline. The wordline consists of a tungsten layer on top of a n type poly. Two charge packets, representing two locally confined bits a and b, can be stored in the nitride film of the oxide–nitride–oxide layer of one flash cell

A cross section of a 63 nm half-pitch Twinflash is shown in Fig. 9. A Twinflash shrink using double patterning should have an asymmetric cell layout geometry, as shown in Fig. 10. Only the width of the MOS channel is reduced, whereas the channel length is kept fixed to accommodate for the high source-drain potential difference during CHE programming. The voltage data of a Twinflash with sub-lithographical dimensions are shown in Fig. 11 and 12 [18]. The flash cells with a width of 45 nm exhibit reasonable programming and erase and can withstand 100 000 cycles without degradation.

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Fig. 10. Sub-lithographical shrink of Twinflash cells

Fig. 11. Electrical results of narrow TwinFlash cells (45 nm width): Programming (a) and erase (b)

Fig. 12. Dependence of Vt on the cycle count. Narrow cells show good endurance behaviour up to 100 kcycles. The window between programmed and erased state remains without significant degradation

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6. Conclusions Next generations of flash will continuously be scaled down. Lithography being stuck at the 193 nm level is not considered an obstacle, since double patterning methods make sub-lithographical dimensions well below 40 nm accessible. However, new materials will be needed to ensure robust operation of the flash devices. For both the conventional FG flash and charge trapping flash, high k dielectrics with large bandgap and low leakage at high fields need to be developed to a maturity good enough for reliable mass manufacture. A charge trapping flash will in addition require high work function materials. A complete set of materials which achieve good data retention, good endurance, and good erase and program levels and write speed, is still to be discovered. Acknowledgements This work was financially supported by the Federal Ministry of Education and Research of the Federal Republic of Germany (Projects Nos. 01M3167 A and 01M3171 A).

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