AC-PLM-1 Data Sheet

AC-PLM-1 Powerline Communication Modem

FEATURES • • • • • • • • • •

OVERVIEW The AC-PLM-1 (PLM-1) is a digital modem implementing a half-duplex transmitter/receiver for powerline communications (PLC). Designed as an ASIC, the device is a very efficient solution for cost sensitive, medium data rate applications. The PLM-1 uses a narrowband FSK (Frequency-Shift Keying) modulation technique. The information is encoded by shifting the frequency of the carrier signal between two discrete values in a very narrow range. By adding a complete set of advanced processing functions to this simple form of modulation, PLM-1 technology offers superior performance in powerline communication. Highly selective filtering and efficient error detection/error correction algorithms make reliable communication in very noisy electrical environments possible. Programmable baud rate and carrier frequency provide flexibility to the user and allow sharing the same powerline medium with other systems and technologies. Protocol-neutral technology allows transporting multiple protocols within one powerline network and enables applications to use more than one protocol.

• • • •

Very robust narrowband FSK modulation Programmable transmission rate from 100 bps to 30,000 bps Programmable communication frequency from 50 to 500 kHz Complete Media Access Control (MAC) logic CSMA/CD type collision detection and resolution Programmable automatic preamble generation Programmable automatic packet-priority management with four levels Error detection (CRC 16) High-efficiency Forward Error Correction (FEC) Full transaction-type management using unacknowledged and acknowledged messages Nibble-oriented efficient data encoding/decoding Parallel and SPI interfaces Protocol neutrality RoHS compliant

APPLICATION EXAMPLES Thanks to its low cost and high performance, the PLM-1 modem offers solutions in a wide variety of PLC applications, for home and commercial buildings, industry and utilities. Building Automation Solutions:

• • • •

Lighting systems HVAC systems Security systems Clocks/sensors

Utilities Solutions:

• • • • •

Automatic Meter Reading (AMR) Load Shedding Remote Diagnostic Street Light Monitoring Traffic Light Controls

Ariane Controls 2145 Chemin Sainte-Foy, suite 22 • Québec City, Québec G1V 1S1 • Canada Tel: 1 418 874 1919 • Fax: 1 418 872 4348 • www.arianecontrols.com • [email protected]

AC-PLM-1

Data Sheet

ELECTRICAL SPECIFICATIONS Symbol

Parameter Input Low-Level Voltage (3V TTL or 5V TTL Tolerant) Input High-Level Voltage (3V TTL or 5V TTL Tolerant) Output Low-Level Voltage Output High-Level Voltage

VIL VIH VOL VOH

Min.

Typ.

Max.

Unit

0.8

V

2.0

V 0.4

V V

2.4

ABSOLUTE MAXIMUM RATINGS Parameter Ambient operating temperature Storage temperature Junction temperature Power dissipation Maximum DC current source by any VDD or VSS pin Output current Maximum operating clock frequency

Ratings -40 to 85°C -55 to 125°C 88°C 33 mW ±28 mA ±3 mA 20 MHz 1

RECOMMENDED OPERATING CONDITIONS Symbol VDD

Parameter Supply voltage

Min. 3.0

FOSC

Clock frequency

4.0

Baud Fc TA

Baud rate Communication center frequency Ambient temperature

0.100 50 -40

Typ. 3.3

25

Max. 3.6 See chart below 30 500 85

Unit V MHz kbps kHz °C

Maximum clock frequency versus the communication center frequency 20,000 18,000

Max Fosc (MHz)

16,000 14,000 12,000 10,000 8,000 6,000 4,000 50

160

200

500

Fc (kHz)

1

According to the chart.

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AC-PLM-1

Data Sheet

SCANEN

CFGD

VSS

VSS

RESET

VDD

VDD

TXEN

TXOUT

RXIN

TXING

33

32

31

30

29

28

27

26

25

24

23

PACKAGE PINOUT

RD/PCKPOL

TEST

42

14

D4/MISO

TEST

43

13

D3/MOSI

TESTEN

44

12

D2/PBUSY

11

STRB/SCLK

15

D0/PDAV

16

41

D1/LBUSY

40

TEST

9

TEST

10

CS

VSS

17

8

39

7

OE

TEST

VDD

TEST

18

MCLKI

RSV

38

6

19

5

37

VSS

PORTSEL

TEST

VDD

TEST

4

CSPOL

20

3

21

36

INT

35

HSK

TEST

2

RXING

MCLKO

22

1

34

CFCLK

TEST

PINOUT DESCRIPTION Pin No. 1 2 3 4 5, 8, 27, 28 6, 9, 30, 31

Name CFCLK MCLKO INT 2 HSK 2 VDD VSS

7

MCLKI

10

D0/PDAV 2,3

11

D1/LBUSY 2,3

12

D2/PBUSY 2,3

13

D3/MOSI 2,3

14

D4/MISO 2,3

15

RD/ PCKPOL 2,3

2

Pin with a permanent 50kΩ pull-up resistor.

3

5V tolerant pin.

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Description Carrier frequency clock (Fcarrier). Master clock output (Fosc). This pin outputs an image of MCLKI. Interrupt. This pin can be configured to be active-low or active-high. Handshake. HSK provides a high impedance state when CS is deactivated. 3.3V power supply terminals. Ground terminals. Master clock input (Fosc). This pin is designed to be driven by an external oscillator or microcontroller. Do not connect a crystal to this pin. Parallel port: Data I/O 0: Data Available. SPI port: Data Available. PDAV is active high. Parallel port: Data I/O 1: Line busy SPI port: Line Busy. LBUSY is active high. Parallel port: Data I/O 2: Port Busy. SPI port: Port Busy. PBUSY is active high. Parallel port: Data I/O 3. SPI port: MOSI - Master Output / Slave Input (serial data input). Parallel port: Data I/O 4. SPI port: MISO - Master Input / Slave Output (serial data output of the PLM-1). Parallel port: Read/Write control signal. SPI port: Clock Polarity.

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AC-PLM-1

Data Sheet

Pin No.

Name

16

STRB/SCLK 2,3

17

CS 2,3

18

OE 3

19

RSV 3

20

PORTSEL 2,3

21

CSPOL 2,3

22

RXING

23

TXING

24 25

RXIN 3 TXOUT 3

26

TXEN 3

29

RESET

32

CFGD

33

SCANEN 4

34-43

TEST

44

TESTEN

Description Parallel port: READ or WRITE strobe signal. SPI port: Serial Clock. The maximum frequency of SCLK is Fosc/4. Chip-Select for parallel and SPI ports. This pin can be configured to be active low or active high. Output Enable. This signal can be used to control external tristate buffers for the data lines D0-D4. Reserved (leave unconnected, do not connect to power or ground) Communication port type selection. High to select the parallel port. Low to select the SPI port. Chip-Select Polarity. When this pin is high, CS is active high. When it is low, CS is active low. Receiving. This pin is asserted Low when the PLM-1 is receiving a packet. This pin can drive a LED directly. Transmitting. This pin is asserted low when the PLM-1 is transmitting a packet. This pin can drive a LED directly. Receiver Input. Transmitter Output. Transmitter Output Enable. Asserted high when the PLM-1 is transmitting. This pin can be used to put the external power amplifier into a low-power mode when the PLM-1 is not transmitting. Logic Reset input. Asserting this terminal low resets the internal logic. Configuration Done. The PLM-1 asserts this pin high when it has successfully received and verified the CRC of its configuration data. Test Control input (for Ariane Controls internal use only). In normal operation, this pin must be tied to ground. Test outputs (for Ariane Controls internal use only). In normal operation, leave unconnected, do not connect to power or ground. Test Control input. This input is used in manufacturing test of the PLM-1 (for Ariane Controls internal use only). In normal operation, this pin must be tied to ground.

Communication port

BLOCK DIAGRAM OF PLM-1 POWERLINE TRANSCEIVER

4

Pin with a permanent pull-down resistor.

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AC-PLM-1 FUNCTIONAL DESCRIPTION

Data Sheet interrupt pin is asserted and will remain so until the host reads the data.

Internal Operation

Configuration

The internal structure of the PLM-1 modem consists of four main blocks, as shown in the figure above. The communication port is used to transfer data and control codes with the host. The clock generator is used internally to set the timings and communication frequencies. The demodulator, or receiver, samples the input signal on the RXIN pin, decodes it and feeds it to the communication port. The modulator, or transmitter, receives data from the communication port and transfers them on the output signal pin (TXOUT).

After power-up, the PLM-1 must be configured. After receiving a Reset command, the modem considers the next 19 bytes it receives as its configuration values. The Ariane Controls PLM-1 Configuration Tool software provides an easy way to compute the configuration parameters according to the user’s application.

The PLM-1 modem is based on a patented technique for modulating the binary information on a frequency shift keying (FSK) carrier in a very narrow band. The digital data is encoded in a binary signal whose frequency is shifted between two discrete values: F0 for logic 0 and F1 for logic 1. In operation, the transmitter waits for the host to load the first outgoing bytes of the packet to transmit. After a priority-queuing wait time, the PLM-1 automatically transmits a preamble in order to gain access to the communication channel. This preamble does not carry any information and is used to detect simultaneous attempts at transmission by other devices. When the PLM-1 gains access to the channel, it transmits a series of synchronizing symbols followed by the host data, while automatically adding error correction codes. The packet is ended with a CRC-16 value, calculated during the entire transmission process. The receiver monitors the medium continuously to determine the line condition. When a signal is detected, the PLM-1 receiver synchronizes to the incoming data and then starts to decode it. Decoded data is then directed to the communication port. After verifying the value of the CRC-16, the PLM-1 transfers the End of Packet to the host, which can start processing the received data according to the protocol being used. The PLM-1 modem needs an external clock signal (MCLKI) that ranges from 4 to 20 MHz in order to provide the operating frequency FOSC. This frequency is used by the communication port and the receiver to sample and validate the incoming data.

Interfacing with the CPU The PLM-1 communication port supports a parallel and a SPI interface. Which one to use depends on the circuit design as well as the capabilities of the CPU. In both cases, a master-slave design must be used, in which the PLM-1 acts as a slave. The PORTSEL pin enables the selection of the interface. In either mode, the clock is provided by the host and the data is synchronized internally to the MCLKI clock. Each time the PLM-1 has to transfer information to the CPU, the

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Packet Format The PLM-1 can use any protocol to transmit information. However, since it uses half-duplex communication, it is recommended to transmit packets less than 45 bytes in size so the medium is not blocked for a long time when a module is transmitting. The only constraint concerning the packet format is that it has to start with a Control Character and end with an End of Packet nibble.

External Components Only a few external components are required to complete the functionality of PLM-1, enabling designers to easily build high-performance powerline communication devices: • Microcontroller, to implement the functionality of the application. • Analog Front End, for signal conditioning in transmission and reception (including filtering and amplification). • Coupling unit, to couple the modulated signals with the power lines and provide safety isolation and protection. • Power supply, to provide suitable power to all components.

DEVELOPMENT TOOLS To help the users of PLM-1 modem to easily integrate the chip into their project, Ariane Controls offers a full range of development tools. • Evaluation boards and easy-to-use software allow for both evaluating and developing PLM-1-based applications. • PLM-1 User Manual provides complete design and application information. • Firmware libraries and sample codes are designed for easy start-up. • Technical support and design review are available to help you succeed.

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AC-PLM-1

Data Sheet

MECHANICAL PACKAGE DATA

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AC-PLM-1

Data Sheet

ORDERING INFORMATION Product number: AC-PLM-1 For further information on Ariane Controls technology and products, please visit our web site: www.arianecontrols.com Sales: [email protected]

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