DOI 10.4010/2015.464 ISSN2321 3361 © 2015 IJESC

Research Article

October 2015 Issue

Development of a Low Cost and High Performance System on Chip Embedded Logic Analyzer Izzeldin Ibrahim Mohamed Faculty of Electrical and Electronics Engineering, Universiti Malaysia Pahang, 26600 Pekan, Pahang, Malaysia [email protected] Abstract: As the complexity of digital system increase drastically from time to time, debugging a digital system has become a challenging task. Usually, defects detection in most digital design are simulated before it is fabricated. As the scale of the logic designs increased, hardware defects are difficult and time consuming to model in simulation. As the result, the debugging theory of using an in-system embedded logic analyzer was introduced. This paper describes the development of a system-on-chip (SoC) proposed as a low cost and high performance PC-based logic analyzer. It is implemented on an Altera Cyclone II FPGA DE1. Besides, the logic analyzer has 16 independent channels and operates at frequency up to 100MHz. The analyzer is communicates to PC through an RS232 serial communication. This allows user to configure the acquisition parameter and visualize the data through a user-friendly graphical user interface (GUI). A main inspiration for this paper is to attain an efficient and free in-system logic analyzer autonomous from any FPGA platform. It can be used in any FPGA, even the designs of ASICs and SoCs. Keywords: Logic Analyzer, FPGA, SoC, VHDL, Verilog I. INTRODUCTION Logic analyzer is an electronic instrument which is used to verify other digital system [1]. Designed for the purpose of debugging and troubleshooting, logic analyzer functions to monitor and measure the performance of digital system through tracing the data flow and present it in an easily readable format [2]. Although oscilloscope can perform many function of logic analyzer, logic analyzer is more suitable to operate in digital environment. It has the capabilities to display relative timing of a large number of digital signals which are too fast to be observed by human eye and can be configured to work with voltage level compatible to LVTTL and LVCMOS. It detects logic analyzer threshold level but does not measure the analog detail [3]. Therefore, logic analyzer is used to examine and analyze the signal in a digital electronic system through logic state demonstration. There are distinct categories of logic analyzer available in the market including the standalone logic analyzer and PC-based logic analyzer. The choice of logic analyzer depends on user budget and working requirement. However, the normal price of a logic analyzer is expensive [3] and too high to be affordable in universities and colleges [4]. The project aims to develop a system-on-chip (SoC) as a low cost and high frequency performance PC-based logic analyzer using Altera Cyclone II FPGA. The PC-based logic analyzer implemented able to evaluate digital devices at frequency up to 100MHz, 16 channels which act as either input or state clock in different operation mode. The analyzer also has a graphical user interface designed to configure the acquisition parameter according to the nature of system under test (SUT) for data visualization

II. DESIGN ARCHITECTURE The logic analyzer design consists of custom components design, utilization of NIOS II processor system and the design of GUI. The functional block diagram is shown in Figure 1. Altera DE1 board

Cyclone II FPGA Memory (RAM) Reset

NIOS II

Controller

Trigger Circuit

Micro-UART

Clock Selector

Data Acquisition CIrcuit

Computer GUI

System UnderTest (SUT)

FIGURE 1 FUNCTIONAL BLOCK DIAGRAM OF THE SYSTEM ARCHITECTURE The system architecture consists of custom modules denoted as data acquisition circuit, trigger circuit, memory modules, clock selector and controller selector. These modules are designed using Verilog hardware description language (HDL). A. CUSTOM MODULES Data Acquisition Module: The data acquisition circuit acquires the data of SUT using a 16-bit register. User is able to

1896

http://ijesc.org/

choose the sampling clock edge which is used to trigger the data sampling either with a positive or a negative clock edge. Trigger Circuit: Logic analyzer uses variety of trigger ways to analyze a digital system [4]. The trigger circuit functions to enable user to capture data with certain state. Post-triggering is implemented where the data is masked with certain value using Trigger Mask defined by user. When the masked value is equivalent to trigger value, trigger signal will be sent to start storing data in the allocated memory. Memory Module: The internal RAM available on DE1 board is used to store the data capture. A 2-port RAM is instantiated using the MegaWizard Plug-In Manager. The memory block defined able to store 4KWords of data and each consists of 16 bits. Once the trigger is met, the memory module starts to store the data until the memory full. Clock selector: Used to select the clock driving the data acquisition circuit. During the timing analysis, internal clock is chosen to drive logic analyzer. While during the state analysis, external clock is chosen from one of the sixteenchannel inputs. Besides, a frequency divider is used to step down the internal clock frequency in timing analysis using equation (1).

Clock generation: The oscillator of Altera DE1 board provides a 50MHz clock signal. The clock input is connected to the phase lock loops (PLL) as a source clock for PLL circuit [7].The PLL circuit will generates 100MHz clock for NIOS II system. UART-RS232 serial communication interface: Used for data communication between the personal computer GUI and the logic analyzer hardware. The baud rate utilized for the serial connection is 115200 bps with 0.01% of baud error. There are 8 data bits and 1 stop bit transferred every cycle. Graphical User Interface: The GUI written in C# programming is designed using Microsoft Visual Studio 2010. The functions of the user interface are to allow user to configure the acquisition parameter and visualize the data capture during the acquisition process. User can configure the parameters such as the analyzer's mode, trigger clock edge, internal clock sampling rate, external clock channel, and trigger conditions. On the other hand, the data is displayed in timing waveform and states list. Figure 2 shows the main window of GUI developed while Figure 3 shows the states list table available in the GUI.

(1) Controller: Is a finite state machine (FSM) which issues the control signals and control the sequence of the acquisition hardware. B. NIOS II PROCESSOR SYSTEM A Nios II processor system is equivalent to a computer on a chip [5]. It consists of Nios II processor core, Avalon interconnection fabric, Altera PLL, UART-RS232 serial connection and other peripherals. The system is instantiated using the SOPC builder available in Quartus II software. FIGURE 2 PROPOSED GUI MAIN WINDOW

Nios II processor: Is a general-purpose reduced instruction set computer (RISC), 32-bit configurable soft-core processor [5]. It has 4Kbytes of cache instructions and uses Joint Test Action Group (JTAG) level 1 for programming and debugging of the software on the development kit. With maximum 100MHz clock, Nios II processor can perform up to 64 million instructions per second (MIPS). In addition, on-chip peripherals and interfaces to off-chip memories and peripherals can be access using Nios II processor. Avalon Interconnection Fabric: Avalon Memory-Mapped (Avalon-MM) interface is a high-bandwidth interconnection structure used to connect the master and slaves components in Nios II processor system [6]. SOPC builder generates the Avalon interconnect fabric and guarantee the signals are routed correctly between CPU, on-chip memory, SDRAM, UART RS232, JTAG UART, custom components and other peripherals.

FIGURE 3 STATES LIST TABLE OF THE GUI

1897

http://ijesc.org/

III. SYSTEM DESIGN METHODOLOGY The developed system consists of both hardware and software design. The hardware is designed using a modular hierarchical approach to manage its complexity [8]. Complex design is divided into several modules with smaller level of complexity using both Top-Down and Bottom-Up design perspective [9]. Figure 4 shows the block diagram of the proposed logic analyzer hardware using register transfer level (RTL) design. The design consists of a control unit (CU) and a data-path unit (DU). The CU is a FSM which controls the flow of the analyzer acquisition operation performed by DU. While the DU consists of a data acquisition circuit, a trigger circuit, a data storage circuit and a clock selector. After the completion of RTL design, the acquisition hardware is connected to the NIOS II processor by means of Avalon-MM interconnection fabric. This forms the complete SoC as shown in Figure 5.

sampled and stored in the register upon the clock edge. Figure 6 shows the block diagram of data acquisition circuit.

FIGURE 6 DATA ACQUISITION CIRCUIT Trigger circuit: Used to enable user to capture sample with certain data. Data is masked with certain value using Trigger Mask defined by user. When the masked value equivalent to the trigger value, trigger will be sent to start storing data in the allocated memory. This situation is best known as posttriggering where data is captured after certain data state. The block diagram of trigger circuit is shown in Figure 7.

FIGURE 4 RTL DESIGN OF THE PROPOSED LOGIC ANALYZER

FIGURE 7 TRIGGER CIRCUIT

FIGURE 5 COMPLETE BLOCK DIAGRAM OF SOC LOGIC ANALYZER Data Acquisition Circuit: constructed using a simple 16-bit register. With a positive edge-trigger flip-flop and a negativeedge trigger flip-flop, user can choose to sample the data in either positive or negative clock edge. Thus, the input data are

Memory Module: Data storage circuit that implemented using the internal RAM available on DE1 board. A 2-port RAM is instantiated which contains of 4096 memory location. Each location in the memory stores 16-bit data. Thus, the memory block is able to store 4KWords of data and each consists of 16 bits. The memory block constructed using 16 M4K was

1898

http://ijesc.org/

instantiated using the MegaWizard Plug-In Manager as shown in Figure 8. The block diagram of data storage circuit is also shown in Figure 9.

FIGURE 10 CLOCK SELECTOR MODULE

FIGURE 8 MEMORY: MEGAWIZAED PLUG-IN MANAGER

FIGURE 11 EXTERNAL CLOCK SELECTOR MODULE Control Unit: After the Data Unit (DU) design, the ASM chart is elaborated to derive the Control Unit (CU) of logic analyzer. Figure 12 show the block diagram of the CU.

FIGURE 12 CONTROL UNIT MODULE

FIGURE 9 MEMORY BLOCK DIAGRAM

Clock selector: Used to select the clock driving the data acquisition hardware. The clock selector module consist of two selectors, namely internal clock and external clock selectors as shown in Figure 10. During timing analysis, internal clock is chosen to drive the data acquisition system while during state analysis, external clock is chosen from one of the sixteen-channel input to drive the data acquisition hardware. Figure 11 shows the block diagram of external clock selector

The hardware setup involves the design of a data acquisition hardware and an external system under test (SUT). SUT is designed using Verilog Hardware Description Language (HDL). A rainbow cable is used as probes of the logic analyzer connect to the SUT and acquire sample from SUT. The SUT consists of the pseudorandom binary sequence (PRBS) generator. PRBS generator is designed using Verilog HDL and implemented on Altera DE2 board to acts as an external circuit. Similar to real random number, PRBS is independent in the sense that values ai element is independent of the value of any other elements. It is deterministic and after N elements, it starts to repeat itself. The proposed SUT is

1899

http://ijesc.org/

generated using a Galois linear feedback 16-bits shift register (LFSR) as shown in Figure 13 and its RTL block diagram shown in Figure 14.When the SUT is clocked, the taps are XORed with the output bit before they are stored in the next position while the bits that are not taps are shifted one position to the right unchanged.

FIGURE 13 16-BITS GALOIS LFSR

A. TMING ANALYSIS For timing analysis, analyzer is configured to timing analysis mode. The 16-bit PRBS generator is used as the SUT to verify the function of timing analyzer to sample periodically with and without trigger enabled. Timing Analysis without Trigger Enable: With the 16-bit PRBS generator acts as the SUT, a set of pseudorandom number were generated. The data are sample from SUT using 100MHz sampling frequency trigger disable. Figure 15 show the timing analysis result acquired from the SUT. Since the PRBS value is deterministic, the data displayed in logic analyzer in compared to the reference result generated using C programming language. The reference result are shown in Figure 17. The data acquired by logic analyzer are proven to be the same as the reference results.

FIGURE 15 TIMING ANALYSIS: 100MHZ WITHOUT TRIGGER

FIGURE 14 RTL Block Diagram of the 16-Bits Galois LFSR IV. RESULTS AND DISCUSSION The proposed logic analyzer developed able to operate as both timing analyzer and state analyzer. Thus, these two type of analysis have been evaluated to prove the functionality of logic analyzer. The analysis includes the timing analysis and state analysis. Reference output results of the SUT are provided to verify the correctness of the system designed.

FIGURE 16 TIMING ANALYSIS: REFERENCE RESULT OF 16-BITS PRBS Timing Analysis with Trigger Enable: Using the same SUT, logic analyzer performed another timing analysis with trigger enabled. The configurations of the timing analyzer are shown in Figure 17. The sampling rate is set to 50MHz to save the data storage and sample more data from the SUT without data

1900

http://ijesc.org/

loss. Besides, the trigger value is set to 3B7C16 which is the second last result from the previous analysis. The data acquired is shown in Figure 18. It can be noticed that using the post-trigger condition, the data acquired after the trigger value. This feature is essential in debugging process to trace the error exist only in certain time.

From Figure 20 and Figure 21, it can be determined that the state analyzer able to acquire any data from the SUT even though the value is random. A proper state clock defined is essential to acquire data in state analysis mode.

FIGURE 20 STATE ANALYSIS: REFERENCE RESULT

FIGURE 17 TIMING ANALYSIS: CONFIGURATION ANALYSIS WITH TRIGGER

FIGURE 18 TIMING ANALYSIS: 100MHZ WITH TRIGGER B. STATE ANALYSIS For state analysis, the analyzer is configured to state analysis mode. The 8-bit PRBS generator is used SUT to verify the function of state analyzer. The clock driving the SUT is input via the data channel 8 to act as a state clock. The configurations of the state analyzer are shown in Figure 19.

FIGURE 19 STATE ANALYZER CONFIGURATION Using the external state clock from SUT, the data capture by the state analyzer is shown in Figure 20. Since the 8-bit analyzer repeat itself every 255 sample, thus only 1 cycle of data captured are shown. The result is compared with the reference result as shown in Figure 21.

FIGURE 21 STATE ANALYSIS: RESULT V. CONCLUSION A low-cost and high-frequency performance PC-based logic analyzer has been developed as a SoC using an Altera Cyclone II DE1 board. The proposed acquisition hardware with 16 channels able to evaluate the digital system at frequency up to 100MHz and operates as either a timing analyzer or a state analyzer. Post-trigger feature included also enables the proposed analyzer to trace the particular section of output from digital system by setting the trigger condition. Besides, the GUI has been successfully designed to configure the acquisition parameters and to visualize the data of all 16 channels. The proposed PC-based logic analyzer has been verified to function flawlessly in all 16 channels and it is able to sample the data at the maximum clock rate of 100MHz. The validation of system specification was successful in entire test environment where the proposed system is verified using different SUT and tested under different configurations. Furthermore, the logical resources used are less than 51% of the total available. The memories embedded (M4K) used are 75% and the total pin used are 33% out of the total 315 pins

1901

http://ijesc.org/

ACKNOWLEDGEMENT This research was supported by Universiti Malaysia Pahang, through the Fundamental Research Grant Scheme (FRGS) funded by Ministry of Education (RDU 140129). REFERENCES 1.

Garcia, L., A. Gonzalez, H.Moreno and G. Jacuenod. Remote logic analyzer implemented on FPGA. IEEE Procedings of Argentina Schools of MicroNanoelectronics, Technology and Applications, Sept. 2008, pp 103-106.

2.

Farnbach, W. A. (1975). "Logic State Analyzers-A New Instrument for Analyzing Sequential Digital Processes.". IEEE Trans. Instrumentation and Measurement, vol 24 , no. 4, pp. 353-356, 1975.

3.

Gu, B., Q. Lu and Y. Liu. (2010). A DAQ Board Based Logic Analyzer Design. International Conference on Electrical and Control Engineering (ICECE). 25-27 June. IEEE, 4594-4597.

4.

Zhao, Z. (2010). Data Processing Technology of Virtual Logic Analyzer Based on FPGA. 2010 International Conference on Digital Manufacturing and Automation (ICDMA). 18-20 Dec 2010. IEEE, 458-460.

5.

Altera Corporation. NIOS II Processor Reference Handbook Version 11.0. San Jose: Altera. May 2011

6.

Altera Corporation. SOPC Builder User Guide. San Jose: Altera. Dec 2010.

7.

Altera Corporation and Terasic Technologies. DE2-70 Development and Educational Board User Manual Version 1.01. San Jose: Altera. 2007.

8.

W.Wolf, "FPGA-Based System Design", Prentice Hall, 2004.

9.

F. Plavec, “Soft-core Processor Design”, Degree of Master of Applied Science, Department of Electrical and Computer Engineering University of Toronto, Toronto 2004.

1902

http://ijesc.org/