A Novel Method to Prepare Wafers with Very Low COPs for Bonded SOI

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A Novel Method to Prepare Wafers with Very Low COPs for Bonded SOI Overview The adoption of silicon-on-insulator (SOI) wafers is clearly part of the future of advanced semiconductor manufacturing, particularly in extending planar CMOS technology beyond sub-50nm gates. Yet, today the cost of SOI wafers is still a barrier for some applications. Presented here is a more cost-effective method — using high heating and cooling rates in a sequential hydrogen-argon rapid anneal — for producing silicon wafers, with low crystal defect counts, used to fabricate SOI wafers. Silicon crystals prepared using the Czochralski (Cz) method and high pulling rates are grown under vacancy rich conditions, resulting in agglomeration of vacancies and formation of crystal originated particles (COPs) [1]. COPs have the shape of 50nm to 150nm octahedral voids. Higher crystal pulling and cooling rates yield high COP densities and smaller COP sizes in crystals. In addition, the doping nitrogen added to a growing silicon crystal enhances oxygen precipitation and results in a high density of smaller COPs in the wafer [2]. The wafer-finishing process (i.e., slicing, lapping, grinding, rough and finish polish, and chemical cleaning) exposes and delineates COPs on a wafer's surface. COPs are typically detected by laser inspection tools (e.g., KLA-Tencor inspection tools using 488nm lasers have a silicon penetration depth of ~0.5µm) and quantified as localized light scatterers (LLSs). COPs and SOI One of the reasons for better control of COPs in wafers is their effect on silicon-on-insulator (SOI) wafers. For example, the presence of COPs in silicon wafers used to fabricate SOI substrates plays a role in the specification of the final substrate. Using a laser inspection tool, COPs on the surface of an SOI "handle" wafer, which only supports the SOI structure, often result in inflated light particle defect (LPD) readings during particle inspection of final bonded SOI products. This problem becomes more pronounced with decreasing thickness of the top silicon layer, as industry demand shifts to thin (i.e., ≤ 0.15µm) and ultrathin (i.e., ≤0.07µm) SOI layers. In another example, surface COPs also cause microvoids at the bond interface [3] and can create defects, such as micro-cracks in an SOI layer after CMP processing or peeling and delamination in the bonding interface during cleaving. COPs control There are three conventional approaches to decreasing — or completely eliminating — the density of COPs in silicon wafers: z

z

A solution that leads to complete elimination of COPs on the surface and in the bulk of silicon wafers is suppression of defects during crystal growth (i.e., "perfect crystal"). A second option grows crystals with very small COPs using high pulling and cooling rates, and by applying nitrogen doping. Surface and bulk COPs are subsequently dissolved by hightemperature annealing in argon or hydrogen. The depth to which COPs are annealed extends 2–

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A Novel Method to Prepare Wafers with Very Low COPs for Bonded SOI

z

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10µm under the wafer surface and is determined by the sizes of COPs in the initial crystal and by the temperature and time of the anneal. A third option deposits a thin epitaxial film (i.e., 0.5–5µm) to cover COPs on the wafer surface.

Wafers prepared by the first approach would be ideal candidates for bonded SOI donor wafers, allowing for multiple reuse of a given wafer after cleaving, thus lowering cost of the final SOI product.

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Figure 1. Process cycles used during short annealing experiments. The last two approaches require a batch furnace or epitaxial reactors in addition to the standard equipment needed to produce polished wafers. This adds considerable cost to silicon wafer manufacturing (in particular for 300mm wafers) and inevitably increases the cost of the SOI product. A fourth alternative Through our research, we have found that by using higher pulling and cooling rates (i.e., >1 mm/min) and a short hydrogen-argon sequential anneal performed in a single-wafer annealing furnace, we were able to produce lower-cost and low LPD wafers [4]. This new process is well suited for producing 200mm and 300mm silicon wafers used in bonded SOI applications for which handle wafers with COPs-free surfaces are needed to achieve a high-quality top SOI layer and bonding interface.

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Figure 2. COP counts (LPD ≥0.095µm) on pre- and post-anneal wafers from crystals A and B using a) a 100%-hydrogen anneal and b) a sequential hydrogen-argon anneal. To compare our new method with a more conventional approach, we prepared two sets of 200mm p{100} Cz wafers from crystals produced by two different growth histories: Crystal A was prepared with a pulling rate of 0.85mm/min, crystal B with a pulling rate of 1.1mm/min. The wafers produced from crystal B had a much higher density of COPs than wafers from crystal A. In our test, wafer resistivity was 9–11W-cm and oxygen was 12–15 ppma. We cut all wafers with a small misorientation angle from 100>, measuring this with x-ray diffractometry. We used both ASM and Applied Materials single-wafer epitaxial reactors as our experimental "single wafer furnaces." Large-scale wafer production can be carried out using commercially available rapid thermal annealing furnaces capable of processing both 200mm and 300mm wafers in the same tool.

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A Novel Method to Prepare Wafers with Very Low COPs for Bonded SOI

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In our test process cycles (Fig. 1), the ramp-up and cool-down rates from the 1200°C soak temperature to wafer load-unload temperature were 3–5°C/sec. By using a high ramp-up rate in hydrogen to temperatures >1100°C, the native oxide on the surface of wafers is quickly and completely removed, thus avoiding surface pitting. (We also did annealing experiments with 100% argon ambient, but this resulted in multiple spike-like defects on the surface of wafers and inflated LPD counts. We believe that this was caused by residual moisture in the argon.) Thus, we were able to maintain a uniform, bare silicon surface during the 1200°C soak temperature in hydrogen or argon. We used purified industrialgrade argon and hydrogen with very low amounts of residual impurities. We imaged pre- and post-anneal COPs with atomic force microscopy (AFM) and used laser inspection tools to determine the location, size distribution, and density of COPs. The combined action of dark narrow (DNN) and dark wide (DWN) channels in the KLA-Tencor SFS SP1 laser inspection tool helped to decrease the detection limit for surface LPDs to ≥0.095µm. We knew from previous experiments that the DNN channel detects shallow post-anneal COPs with high sensitivity, so the vast majority of defect counts that we detected on wafers with our inspection tool, before and after annealing experiments, were in the 0.095–0.25µm bins. Process proof Overall, we found that our process of introducing hydrogen and argon in the right sequence to modify surface morphology yielded wafers with surface haze lower than that on wafers annealed with hydrogen alone and comparable to polished wafers [4]. We also found that our sequential anneal was superior in reduction of LPD counts, compared to the 100%-hydrogen process (Fig. 2). LPD counts on wafers after the hydrogen-argon sequential anneal decreased by 92%, compared to only a 60% decrease when using a 100%-hydrogen anneal. Our AFM scans indicated that the introduction of different gases during short sequential anneals did produce a terrace structure on wafers different from these structures observed after a 100%-hydrogen anneal [4]. As expected, AFM scans of annealed surfaces showed that 100%-hydrogen-annealed wafers have straight terraces. AFM images of wafers after the hydrogen-argon sequential anneal showed wavy-like terraces. The variations in the shapes of terraces can be explained by the role that different gas ambients play during the surface reconstruction at high temperatures and breakage of silicon bonds [4]. We also found that the surface micro-roughness measured by AFM on wafers after sequential annealing is comparable to values measured on epitaxial wafers and on 100%-hydrogen-annealed wafers [4].

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Figure 3. AFM images of COPs on wafers after a) short 100%-hydrogen annealing and b) short

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A Novel Method to Prepare Wafers with Very Low COPs for Bonded SOI

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hydrogen-argon sequential annealing. Our AFM measurements showed that a short hydrogen-argon sequential anneal creates very shallow, dish-like structures at the location of original surface and subsurface COPs; these had an average lateral dimension of 2µm and vertical depths of 1.5nm (Fig. 3). These small concave regions were difficult to find and distinguish from neighboring areas without use of coordinates from our laser inspection systems. Similar structures were observed on wafers annealed in a batch furnace with 100%-hydrogen [5], and also after deposition of epitaxial layers up to 4µm thick [6]. Original subsurface COPs opened during etching with 100% hydrogen were identified as the source of added LPD counts on wafers annealed in 100% hydrogen [4]. Uncovered and annealed subsurface COPs were then transformed into the dish-like structures. We have also found that decreasing the high temperature hold time will further reduce the overall cost of the hydrogen-argon sequential annealing process. We performed sequential annealing tests at 1200° C where times in argon were decreased from 2 min to 30 sec (Fig. 1b). The tests reconfirmed the advantages of using this new method for reducing LPDs and producing wafers with a surface haze level similar to polished wafers [4]. For example, an annealing efficiency for surface COPs during hydrogen-argon sequential annealing that included only a 30-sec, high-temperature hold in argon corresponded to an efficiency obtained after a 2-min, high-temperature hold in hydrogen using a 100%-hydrogen anneal. The resulting silicon We have found that application of high heating and cooling rates during a short hydrogen-argon sequential anneal in a rapid thermal anneal furnace can simultaneously lead to a magic denuded zone (i.e., MDZ) effect and create an internal gettering (IG) template in the middle of the annealed wafers. IG in donor and handle wafers is later activated during heat treatment and can provide protection for a top SOI layer in case of accidental metallic contamination during production of SOI wafers. After splitting donor wafers to create the top SOI layer, the handle wafers with built-in IG will remain part of the bonded SOI product, and thus provide protection against contamination during IC fabrication. In addition, we estimate that the short hydrogen-argon sequential anneal also anneals near surface COPs located ≤0.1µm under the wafer surface. Wafers can be used as donor substrates for ultrathin bonded SOI products (≤0.07µm SOI layer), eliminating the presence of HF defects in the top SOI layer and helping to achieve a high-quality bonding interface. Acknowledgment MDZ is registered trademark of MEMC Electronic Materials Inc. References 1. V.V. Voronkov, et al., Electrochem. Soc. Proceedings, Vol. 97-22, p. 4, 1997. 2. M. Iida, et al., Electrochem. Soc. Proceedings, Vol. 98-1, p. 855, 1998. 3. M. Itsumi, et al., Jpn. J. Appl. Phys., Vol. 38, p. 5720, 1999. 4. J. Vasat, et al., Electrochem. Soc. Proceedings, Vol. 02-2, p. 254, 2002. 5. R. Schmolke, et al., Electrochem. Soc. Proceedings, Vol. 97-22, p. 4, 1997. 6. L. Fei, et al., Electrochem. Soc. Meeting Abstact, Vol. 99-2, Abstr. No. 1320, 1999. Jiri Vasat received his BS in chemical technology from Technical Univ. in Brno, Czech Republic, and his MS and DSc in materials science and technology from Washington Univ., St. Louis. He is

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A Novel Method to Prepare Wafers with Very Low COPs for Bonded SOI

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marketing manager for microcomponents and emerging market segments at MEMC Electronic Materials Inc., 501 Pearl Dr., St. Peters, MO 63376; ph 636/474-7562, fax 636/474-5190, [email protected]. Tom Torack received his BS in chemistry from Washington University and BS in chemical engineering from University of Missouri, Rolla. He is a research engineer at MEMC. Jiri L. Vasat, Tom Torack, MEMC Electronic Materials Inc., St. Peters, Missouri Solid State Technology March, 2003 Author(s) : Jiri Vasat Tom Torack

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