A MULTI-STANDARD SET-TOP BOX CHANNEL DECODER Nirmal Sohi and P.Glenn Gulak Department of Electrical and Computer Engineering University of Toronto Toronto, Ontario Abstract - Digital transmission and recording technologies such as Direct Broadcasting by Satellite and DVD are revolutionizing the home-entertainment consumer electronics industry. It would be economical and convenient to use a single “set-top box” receiver for mnltiple services. Based on an analysis of the standards for Digital Audio Broadcasting (DAB),Digital Video Broadcasting (DVB) and DVD, a Viterbi decoder and a Reed-Solomon decoder are found to be common channel decoding components that would benefit from co-integration. This paper presents the synthesis-based design and test results of a 62.5 Mbps output rate multi-standard Viterbi decoder implemented in a 035 p n CMOS process.

1. INTRODUCTION Recently developed digital transmission and recording systems are gradually taking the place of older analog broadcasting and recording systems. The growing popularity of digital television broadcasting and DVD illustrate this trend. Consumers generally require a separate device to use each of these digital services, each device processing a different high speed bit-stream. An area currently of great interest is “convergence” of some of these devices into a single integrated receiver. If different services use the same receiver, economies of scale can result in more devices being sold and a lower device cost which benefits both service providers and consumers. In this paper, we consider three digital services which are good candidates for convergence in a set-top box for home entertainment: Digital Video Broadcasting (DVB), Digital Audio Broadcasting (DAB) based on the Eureka 147 standard [4] and Digital Versatile Disc @VD). Three types of DVB are considered in this paper: DVB-Satellite @VB-S) [I], DVB-Terrestrial @VB-T) [2] and DVB-Cable (DVB-C) [3]. The MPEG-2 decoder used in DVB, DAB and DVD systems is one of the receiver’s most complex VLSI cores. Since only a single MPEG-2 decoder would be needed in a multi-standard set-top box, these standards are amenable to convergence. The general concept of a multi-standard receiver has been proposed in [5]. The focus of this paper is on the baseband “channel decoding” components of DVB and DAB, and the baseband “data detection” components of DVD. The objectives are to implement a single reconfigurable hardware architecture that can satisfy the performance requirements of these components while minimizing cost. Section 2

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points out that a Viterbi decoder (VD) and Reed-Solomon (RS) decoder are the common computational elements used in most of the standards in question. Since the VD design requires intemal changes to its structure in order to accommodate different standards, most of the design effort is devoted to the VD as outlined in Section 3. Since DVB-S and DVD are the two most widely adopted digital services in question, performance simulations of DVB-S and DVD are principally used in constraining the Viterbi decoder design. Section 4 gives the requirements that a RS decoder must meet to operate with the considered standards. Section 5 presents VLSI implementation details and test results for the Viterbi decoder.

2. COMMON ELEMENTS OF DVB, DAB AND DVD This section describes the channel decoding and data detection algorithms common to the DVB, DAB and DVD standards. Fig. 1 illustrates the commonalitiesamong the channel decoding components of these standards.

DAB

DVB-T

DVB-S

DVB-C

DVD

To MPEG-2 demultiplexer and source decoder

Fig.I: Channel decoding common elements Ideally, each layer would be realized as a single hardware block. However, the objective here is to focus on the layers common to as many standards as possible. Examination of Fig. 1 reveals that the Viterbi decoder and Reed-Solomon decoder are used in four out of the five standards. These components are complicated and

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costly enough to consider combining into reconfigurable (“soft”) macro-blocks. The next section focuses on the design of a single Viterbi decoder which could operate with DAB, DVB and DVD.

3. VITERBI DECODER DESIGN The Viterbi Decoder (VD) is a hardware implementation of the Viterbi algorithm [7], and consists of four main components: the Branch Metric Generator (BMG), the Add-Compare-Select (ACS) unit, the Survivor Memory Unit (SMU) and an Output Decision Device (ODD) [8]. Certain design parameters of the Viterbi decoder components must be selected through performance analysis. Based on Bit Error Rate (BER) simulations for DVB-S and DVD along with published DAB and DVB-T implementations, the parameters of a Viterbi decoder which could operate with DAB, DVB and DVD standards have been determined [6]. For DAB and DVB, four-bit quantized channel outputs are used, while five-bit input samples are used for DVD. The L1-norm distance metric was selected for the BMG operation in all standards. The ACS unit operates according to modulo-2 arithmetic to avoid renormalization of path metrics [9]. The register-exchange architecture was used for the SMU due to its simplicity and modularity. BER plots and firther details of the Viterbi Decoder design are given in [6]. DVB and DAB convolutional codes could both be accommodated by a single Viterbi decoder with a flexible BMG. Although the DVD readout signal is not convolutionally encoded, it is corrupted by intersymbol-interference (ISI). Since IS1 can be modelled as a Markov process, it can be mitigated by the application of the Viterbi algorithm. IS1 can therefore be removed by a “Viterbi detector”, which is a Viterbi decoder using a specific type of branch metric. To use the same Viterbi decoder for both convolutional decoding and IS1 removal, the architecture of the BMG and ACS units must be made flexible enough to handle both applications. The BMG of the multi-standard Viterbi decoder has been designed to compare the channel outputs to sixteen possible values when operating in DAB or DVB mode. Decoding the rate 1/4 DAB code requires comparing four channel outputs to their sixteen possible expected values. The rate 1/2 DVB convolutional code can be handled transparentlyin this architecture simply by erasing the two unused channel outputs and forwarding four branch metrics to the ACS unit rather than sixteen. The implementation of this operation is described in Section 5. The DAB and DVB convolutional codes are fixed and require 64 states in the Viterbi decoder. However, the number of states to use for DVD IS1 removal is not as clear. The number of symbol intervals used to model IS1 determines the number of states in the Viterbi decoder. Through performance simulations [6], it was found that using a 64-state Viterbi decoder reduces the IS1 significantly (the use of more

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states does not result in any appreciable performance gain). Therefore, the same basic 64-state trellis interconnection structure in the ACS and SMU can be used for both convolutional decoding and IS1 removal. The EFMPlus Run-Length-Limit constraints [101 on the DVD bit stream permit the Viterbi decoder to be modified to reduce the required number of states, while improving performance. Specifically, these constraints imply that the NRZIencoded bitstream must have no fewer than three contiguous identical symbols [6]. Hence, the number of valid states reduces from 64 to 18, and the number of valid transitions reduces from 128 to 26. The trellis representation of the allowed states and transitions is shown in Fig. 2. Sk+l

000000 000001 00001 1 0001 11 001 110 001111 01 1100 011110 011111 100000 100001 100011 1 10000 110001 111000 111100 111110 111111 Fig.2: EFkfplus constrained states and transitionsfim state Sk to state sk+] The DVD sub-block of the BMG calculates the difference between channel output samples and expected samples for the 26 valid branches. The trellis interconnections for DVB, DAB and the unconstrained DVD trellis are identical and ACS cells are interconnected according to this trellis. In the DVD mode, the ACS unit connects the valid branch metrics from the BMG to the corresponding ACS cells and invalid branches are assigned the largest possible branch metric. Thus, in DVD mode, the ACS effectively operates according to the constrained trellis in Fig. 2. In states with only one valid input branch, invalid branches are not

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selected since they have a higher branch metic than any valid branch. Section 5 presents implementation details of the Viterbi decoder.

4. REED-SOLOMON DECODER DESIGN All DVB standards employ the same (204,188) RS code. The DVD standard employs a RS product code using a (182,172) “row” RS code and a (208,192) “column” RS code [13]. The RS-codes for DVD and DVB standards all operate in GF(2*), and are based on a (255,239) RS code. Therefore, the same Galois Field arithmetic units and hardware can be used for different standards. The codes are shortened and punctured as shown in Table 1.

Standard

DVD, row

(182, 172)

5

67

6

DVD, column

(208, 192)

8

47

0

The row RS-code used in the RS-PC for DVD is shortened by 67 symbols and punctured by 6 symbols resulting in a (182, 172) code. These 6 punctured symbols can be inserted and deterministically “erased” at the receiver [I 11. The same basic “error and erasure” correcting RS-decoder can be used for all standards provided the input RS-codewords are pre-processed correctly, by zero-padding them to form the original 255-byte RS-codeword. Therefore, the main considerations in designing a single RS decoder which handles DVB and DVD codes is that it must correct errors and erasures to deal with the punctured DVD RS code, and operate at an input data rate on the order of 8 MB/sec to handle a 62.5 Mbps Viterbi decoder output rate (the output rate of the implemented Viterbi decoder). A complete error-and-erasure correcting RS decoder design based on a modified form of Euclid’s algorithm [12] was functionally tested in Matlab simulations. Performance estimates based on synthesized components of the RS decoder are presented in [6].

5. VITERBI DECODER IMPLEMENTATION A silicon implementation of the Viterbi decoder was produced, and Fig. 3 shows the high level chip architecture based on the design discussed in Section 3.

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erasure

Branch Metric Generator (BMG) metrics

:rich

decision (SMU) AddCompareSelect (ACS) Unit

config. mode clock reset

min. state output bit

Fig. 3: Overall chip architecture

The BMG contains a DVBDAB sub-block which determines the difference between the received and expected channel outputs. Part of the DVBDAB subblock functionality for a single branch metric is illustrated in Fig. 4, where DVBflag is a binary flag indicating whether the Viterbi decoder is operating in DVB mode.

IIchannel- Iexpectedl

:-

Qem

-

IQchannel QexpectedI

/

branch metric

Fig. 4: Functional model for part of a single DVB/DAB branch metric computation

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The erasure flags for the channel outputs are provided by a depuncturing unit, details of which are presented in [6]. The overall BMG also contains a DVD sub-block which outputs the difference between the channel samples and expected samples. Before decoding in DVD mode, the BMG can be configured by reading in the expected channel outputs correspondingto the transitions in Fig. 2. The ACS unit is composed of 64 Select-Add-Compare-Select (SACS)sub-units as in Fig. 5. The SACS sub-unit for state r accepts branch metrics from statesp and q, and the “ACS cell” in the figure carresponds to the traditional ACS operation. These SACS sub-units select branch metrics according to the decoding mode, add the branch metrics to the corresponding path metrics, and select the lowest resulting path metric.

DAB branch metricp, -b DVB branch metricp, --b DVD branch metricpr+ path

DAB branch metricq,

-

ACS

-F

path metric, decision,

DVB branch metricq,._+ DVD branch metric, -b

Decoding mode Fig. 5: Select-Add-Compare-Selectsub-unitfor state “r ’’ using a standard ACS cell

The @-state survivor memory unit (SMU) has a survivor length of 70. Its output is forwarded to the output decision device which determines the state with the minimum path metric, and outputs the correspondingbit from the SMU. Based on bit-true C simulations, the Viterbi decoder was designed in VHDL and implemented in a three-metal layer 0.35 pm CMOS technology. A multiplexed flip-flop scan-chain methodology was used to test for manufacturing faults. The chip was successfully tested at 20 MHz (the maximum speed of the University of Toronto’s HP VXI tester). A photomicrograph of the chip with a floorplan overlay is shown in Fig. 6, with chip characteristicsgiven in Table 2.

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Fig. 6: Mterbi decoder chip layout

Parameter

I

~~

Value ~~~~~~

Process

TSMC 0.35 pm CMOS 3LM

I 25.2 mm2 I

Core area

3.3 V

Supply voltage

62.5 Mbps

Speed I

Table 2: Chip characteristics

6. CONCLUSIONS Consumer electronics for home entertainment is a rapidly growing market with many of the new digital services to the home being specified in industry-wide standards. By taking advantage of similarities between these standards, unified receiver components can be created to reduce overall cost. It was shown that the

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Viterbi decoder and Reed-Solomon decoder were common to most of the standards. Constraints on the Reed-Solomon decoder design were given, and a prototype Viterbi decoder implementation which operated with all of the relevant standards was presented. Since the multi-standard receiver must meet the performance requirements of all relevant standards, the minimum required level of performance is exceeded in certain decoding modes. For example, the Viterbi decoder has more than the minimum required number of input quantization bits for DVB (since DAB requires a higher resolution), and more than the minimum required number of states for DVD (since 64 states are required for DVB and DAB). Since the multi-standard receiver contains a superset of the hardware required for compliance with any individual standard, “extra” hardware resources create the potential for a synergistic performance improvement for all standards. This paper has dealt primarily with a selected set of open standards for emerging digital services. There are many other services which have similar receiver architectures which could be combined. There are many possible receiver combinations; this paper has focussed on a set of standards which are suitable for a home entertainment multi-function set-top box.

ACKNOWLEDGMENTS The authors gratefully acknowledge financial support from the Natural Sciences and Engineering Research Council of Canada, the Canadian Space Agency, and chip fabrication support from the Canadian Microelectronics Corporation.

REFERENCES [13 ETSI standard, “Digital Video Broadcasting (DVB); Framing structure, channel

coding and modulation for 11/12 GHz satellite services”, EN 300 421, 1997. [2] ETSI standard, “Digital Video Broadcasting (DVB);Framing structure, channel

coding and modulation for digital terrestrial television”, EN 300 744, 1997.

[3] ETSI standard, “Digital Video Broadcasting (DVB); Framing structure, channel coding and modulation for cable systems”, EN 300 429, 1998. [4] ETSI standard, “Digital Audio Broadcasting (DAB) to Mobile, Portable and Fixed Receivers”, ETS 300 40 1,2nd ed, 1997. [5] A. Romanowski, 0.Klank, K. Fazel, “Concept of a Multi-standard Receiver for

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Digital Broadcast and Communication Services”, ZEEE Transactions on Consumer Electronics, vol. 43, no. 3, Aug. 1997

[6] N. Sohi, “A Multi-Standard Set-Top Box Channel Decoder”, M.A.Sc. Thesis, University of Toronto, 2000.

[7] G. Fomey, “The Viterbi Algorithm”, Proceedings of the ZEEE, vol. 61, no. 3, March 1973. [8] G . Clark, J. Cain, Error-Correction Coding for Digital Communications, Plenum Press, 198 1. [9] G. Feygin, “A Multiprocessor Architecture for Viterbi Decoders with Linear Speed-up”, MASc. Thesis, University of Toronto, 1990. [lo] K. Immink, “The Digital Versatile Disc (DVD):System Requirements and Channel Coding”, SMPTE Journal, vol. 105, no. 8, Aug. 1996, p. 483-489. [l 11 S . Wicker, Error control systems for digital communication and storage, Prentice-Hall, 1995. [12] H. Shao, T. Truong, I. Hsu, L. Deutsch, “Architecture for time or transform domain decoding of Reed-Solomon codes”, US.Patent US4868828, 1989. [ 131 H. Chang, C. Shung, “A Reed-Solomon Product-Code (RS-PC) Decoder for

DVD Applications”, IEEE International Solid-state Circuits Conference (ISSCC), 1998, p. 390-391.

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