A Fully-Integrated 5GHz CMOS Wireless-LAN Receiver Hirad Samavati

Center for Integrated Systems Stanford University

Outline ❑ Motivation ❑ Introduction to Wireless LAN ❑ Receiver Architecture ❑ Circuit Implementations ❑ Offset Cancellation Techniques ❑ Fractal Capacitors ❑ Measurements ❑ Conclusions

Motivation • Demand for wideband wireless local area network (LAN) - High data rate (> 20Mb/s) - Low cost (CMOS) - Low power

• New released frequency band in US - Unlicensed national information infrastructure (U-NII) band

• Existing frequency band in Europe - High performance radio LAN(HIPERLAN) band

Available Frequency Bands HIPERLAN

5.15

U-NII

5.30

5.35

5.825 GHz

5.725

• U-NII and HIPERLAN frequency bands. 23.5MHz

5.15

5.35

GHz

• Proposed channel allocation for a U-NII band WLAN system. - Compatible with HIPERLAN.

HIPERLAN Receiver Requirements Modulation Maximum signal level Sensitivity Channel bandwidth Spurious emissions 30MHz-1GHz 1GHz-25.5GHz

GMSK -25dBm -70dBm 23.5MHz -57dBm -47dBm

NF < −143.7dBm/Hz − 12dB − (−174dBm/Hz)=18.3dB Sensitivity (-70dBm)/(23.5MHz) Pre-detection SNR Available noise power of the antenna

Receiver Architecture + Differential Input 5.15-5.35 GHz

Σ _

Baseband Buffer

I

LNA Fractal Capacitors Tracking Filter

+

+ Σ

Vc VCO Loop Filter

Charge Pump

Image-Reject PLL

PFD LO2 Buffers

LO1 Buffers Q

fref

PFD

Charge Pump

Program & Pulse Swallow Counters

Loop Filter

I

Q

I

Quadrature VCO

Prescaler N/N+1

Channel Select Bits

Tracking ILFD 2

8

Synthesizer

Baseband Buffer

Q

LO Frequencies 1 ------ ⋅ ω 17 Sig

Satellite downlink

Img.

LO2

16 ------ ⋅ ω 17 Sig

LO1

• Image signal is small.

LO1

÷2

÷8

LO2

Low-power injection-locked frequency divider

• LO2 easily obtained from LO1.

Sig.

Image Rejection

V Out ( f )

Out M3

-----------------V In ( f )

X In

M1

fmin Zf

fimg fsig Frequency

• Series resonance @fImg→ improves image rejection

fmax

Noise Rejection

M3 X In

M1

Cx

Lx

Noise Figure

Parasitic capacitance Cx degrades the noise performance.

Without LX

With LX

fmin

fimg

fsig Frequency

• Parallel resonance @fSig→ improves noise figure

fmax

Solution: Third-Order Filter 2

L5 ⋅ ( C 3 + C 1 ) ⋅ s + 1 Z f ( s ) = -------------------------------------------------------3 C 1 ⋅ C 3 ⋅ L5 ⋅ s + C 3 ⋅ s

C3

L5

ωp = 0 1 ω p = ± --------------------L5 ⋅ C 1 1 -------------------------------------ωz = ± L5 ⋅ ( C 3 + C 1 )

Zf

C1

LNA/Filter Transfer Function log Z f ( f )

1 log  ---------  gm  3

Out 1/gm3 C3 M3

In

L5

M1

C1

fmin

fimg

fsig

fmax

fmin

fimg fsig Frequency

fmax

V Out ( f )

-----------------V In ( f )

Zf

Equivalent Noise Circuit for the LNA Zin

X

M3

Iout

Lg M1 Cx Ls First stage

Second stage

(all noise sources modeled)

V

Rs

2 g1

I

+ −

2 V + s −

(Only drain noise modeled)

+

2 g1

V1

I

Rin1

− G m1 V 1

2 d3

+

Cx

V3 1/gm3 g V − m3 3

Iout

Filter Noise Model C3 Cx

C1

L5

I

2 L5

1 ----------G L5

Simplifies to 2 2 ψI + I   d5 L5

1 – ---------g m5

I

2 d5

Noise Formulas F no – filter = F 1 +

2 2  ω 0   C x 2 - ω 0 4R s γ 3 g do3  ------2-  -------2  ω T   g m3 

F with – ideal – filter = F 1 F tot = F 1 + ψ ⋅ 4R s ( γ 5 g do5 +

2

2  ω0 G L5 )  ------2-  ωT 

2

C 3 ⋅ ω0 = ----------------------------------------------------------------------------, ψ Where 2 2  C3  2 2  ------------------- ⋅ ω 0 + ( G L5 – g m5 )  C x + C 3

and F1 is the noise figure of the first stage defined in: D. Shaeffer and T. Lee, “A 1.5V, 1.5 GHz CMOS Low Noise Amplifier”, IEEE Journal of Solid-State Circuits, May 1997, pp. 745-759.

Receiver Architecture Fractal Capacitors +

Σ _

Baseband Buffer

I

Baseband Buffer

Q

LNA Tracking Filter

+

+ Σ

Vc VCO Loop Filter Image-Reject PLL

Charge Pump

PFD

LO2 Buffers

LO1 Buffers Q

I LO1

Q

LO2 Synthesizer

I

Circuit Implementation: LNA and filter LNA

L3

In+

L4

M3

M4

M1

M2

L1

In-

L2 I1 (Const. gm source)

C3

L5

M5 Filter

C1Vc C2

L6

C4

M6 I2 (Const. gm source)

Receiver Architecture Fractal Capacitors +

Σ _

Baseband Buffer

I

Baseband Buffer

Q

LNA Tracking Filter

+

+ Σ

Vc VCO Loop Filter Image-Reject PLL

Charge Pump

PFD

LO2 Buffers

LO1 Buffers Q

I LO1

Q

LO2 Synthesizer

I

Circuit Implementation: First Mixers IF+

LO1

M3

M4

LO1

RF+ RFLO1

M1

M2

LO1

IF-

- A. Shahani, et al, “A 12-mW wide dynamic range front-end for a portable GPS receiver,” IEEE J. Solid-State Circuits, vol. 32, pp. 20612070, Dec. 97.

Receiver Architecture Fractal Capacitors +

Σ _

Baseband Buffer

I

Baseband Buffer

Q

LNA Tracking Filter

Vc

+

+ Σ

Loop Mixer

VCO Loop Filter Image-Reject PLL

Charge Pump

PFD

LO2 Buffers

LO1 Buffers Q

I LO1

Q

LO2 Synthesizer

I

Circuit Implementation: VCO and Loop Mixer Vbias

Loop Mixer

IF+ LO1

M3

M4

LO1

LO1

RF+ RFM1 M2

LO1

IFVbias C3

L5

C1

Vc

C2

M5 VCO

L6

M6 I3

C4

Receiver Architecture Fractal Capacitors +

Σ _

Baseband Buffer

I

Baseband Buffer

Q

LNA Tracking Filter

+

+ Σ

Vc VCO Loop Filter Image-Reject PLL

Charge Pump

PFD

LO2 Buffers

LO1 Buffers Q

I LO1

Q

LO2 Synthesizer

I

Circuit Implementation: Second Mixers To Current Summing Resistors +Out

-Out

+ LO Ib

+In

-In

DC Offsets

Baseband Amp

LO Leakage

Interferer Leakage

LO

Baseband Amp

LO

DC Offset Cancellation Techniques • Capacitive Coupling - Requires a large capacitor

Baseband Amp LO

• Negative Feedback - Nonlinear

Baseband Amp

LO

-a MOS Capacitor

• TDMA offset Cancellation - Requires a large capacitor

Baseband Amp LO

Switch

Traditional Capacitors Gate Capacitance: High capacitance per unit area Nonlinear Requires DC bias voltage Low breakdown voltage Medium Q

Junction Capacitance: Highly nonlinear Requires DC bias voltage Sensitive to process variations Low Q Large temperature variation

Metal to Metal / Poly Capacitance: Linear High Q Small temperature variation Low capacitance per unit area

Thin-Insulator Capacitors: Linear Expensive Not available in standard CMOS

Improving Capacitance Density • Lateral flux improves capacitance density.

• Structures with large periphery are desirable. • Some fractals have finite area but infinite perimeter.

Fractal Capacitor

# of cross-connected layers=4 Horizontal spacing=0.6µm Vertical spacing=0.8µm Capacitance boost factor=2.3

Scalability Unlike conventional parallel-plate structures, the capacitance per unit area increases as the process technologies scale.

Reduction of the Bottom-Plate Capacitance Area is smaller. Some of the field lines terminate on the adjacent plate instead of the substrate. First Terminal

Second Terminal

Second Terminal

First Terminal

Substrate

Improved Matching 6

Number of dice

5

Central sites σcentral=9.4fF (0.2%) 8”

4 m=5.5pF σ=83fF

3

22mm

2 1 0

5.4pF

5.5pF Capacitance

5.6pF

Capacitance distribution across the wafer

CAD Tool Layout

Tech. File

Fractal Lib.

User Input

Field Solver

LGFC

C Ls & rs

Report LGFC Layout Generator for Fractal Capacitors

Receiver Architecture Fractal Capacitors +

Σ _

Baseband Buffer

I

Baseband Buffer

Q

LNA Tracking Filter

+

+ Σ

Vc VCO Loop Filter Image-Reject PLL

Charge Pump

PFD

LO2 Buffers

LO1 Buffers Q

I LO1

Q

LO2 Synthesizer

I

Offset Cancellation Circuit Capacitor Area:131x165µm Capacitance value:15pF Bottom-plate capacitance/terminal:1.2pF Self-resonance frequency:11.3GHz Capacitance density: 700aF/µm2 Capacitance boost factor:3.5

Resistor Area: 103x61mm Resistance value:2.1MΩ Bottom-plate capacitance/terminal:0.3pF Corner frequency 5kHz

Die Micrograph

Die Area:4mm2 Technology:0.24-µm CMOS

Measured Receiver NF 8.0

Noise Figure (dB)

7.8 7.6 7.4 7.2 7.0 6.8 5.15

5.20

5.25 Frequency (GHz)

5.30

5.35

Measured Image Rejection 57.0

Image Rejection (dB)

55.0

53.0

Ch4

Ch5

Ch6 Ch7

Ch8

Ch3 51.0

Ch1 Ch2

49.0 47.0 5.15

5.20

5.25 5.30 Frequency (GHz)

5.35

IP3 Measurement Results Two-tone test (f1=5.263, f2=5.265GHz) 20

Output Amplitude (dBV)

0

-20

-40 IIP3=-7dBm -60

-80 -40

-35

-30

-25 -20 -15 -10 Source Power (dBm)

-5

0

1-dB Compression-Point Measurement 20.0

Output Voltage (dBV)

10.0

0.0 1dB -10.0

-20.0

-30.0 -50.0

-40.0 -30.0 -20.0 Source Power (dBm)

-10.0 -18 dBm

1-dB Blocking Desensitization Point

Blocking Source Power (dBm)

-14

-16

-18

-20

-22 LO1 -24 -700

-500

-300 -100 100 300 Offset Frequency (MHz)

500

700

Measured S11 of the Receiver 0

-5

S11 (dB)

-10

-15

-20

-25 4.0

4.5

5.0 Frequency (GHz)

5.5

6.0

Measured Performance Summary Signal path performance Noise figure Voltage gain S11 Image rejection (filter only) Image rejection (total) Input-referred IP3 1-dB compression point LO1 Leakage to RF LO2 Leakage to RF

Achieved 7.2dB 26dB < -14dB 16dB 53dB -7dBm -18dBm -87dBm -88dBm

Power dissipation Synthesizer Divide-by-8 (for LO2) Signal path Image-reject PLL LO buffers Biasing Total power Supply voltage

25.3mW 6.0mW 18.5mW 3.1mW 5.0mW 0.9mW 58.8mW 1.8V

Implementation Die area Technology Package

4mm2 0.24-µm CMOS 32-pin ceramic flat pack

Required 18.3dB

-21dBm -47dBm -57dBm

Contributions • Implementing the first 5GHz CMOS wireless-LAN receiver. The receiver is: - highly integrated - low power - highly linear and tolerates large blockers

• Developing a novel RF filter topology that: - rejects the image signal - improves the LNA noise figure

• Demonstrating the feasibility of automatic tuning techniques at RF frequencies using a low power image-reject PLL.

Contributions • Implementing a novel capacitor structure using fractal geometries. • Demonstrating the benefits of fractal capacitors including: - area efficiency - linearity - scalability - reduced bottom-plate capacitance - improved matching characteristic

• Developing a CAD tool to automatically generate custom fractal layouts.