sensors Technical Note

A Dynamic Instrumentation Amplifier for Low-Power and Low-Noise Biopotential Acquisition Jongpal Kim 1 and Hyoungho Ko 2, * 1 2

*

Samsung Electronics Inc., Suwon 16678, Korea; [email protected] Department of Electronics, Chungnam National University, Daejeon 34134, Korea Correspondence: [email protected]; Tel.: +82-42-821-5664; Fax: +82-42-823-5436

Academic Editor: Vittorio M. N. Passaro Received: 24 January 2016; Accepted: 4 March 2016; Published: 9 March 2016

Abstract: A low-power and low-noise dynamic instrumentation amplifier (IA) for biopotential acquisition is presented. A dynamic IA that can reduce power consumption with a timely piecewise power-gating method, and noise level with an alternating input and chopper stabilization technique is fabricated with a 0.13-µm CMOS. Using the reconfigurable architecture of the IA, various combinations of the low-noise schemes are investigated. The combination of power gating and chopper stabilization shows a lower noise performance than the combination of power gating and alternating input switching scheme. This dynamic IA achieved a power reduction level of 50% from 10 µA to 5 µA and a noise reduction of 90% from 9.1 µVrms to 0.92 µVrms with the combination of the power gating and chopper stabilization scheme. Keywords: biopotential; dynamic instrumentation amplifier; power gating; alternating input; chopper stabilization

1. Introduction Currently, attempts are being made to perform comfortable and continuous health monitoring in daily life through a wearable system [1–5]. Many biosignals, including electrocardiogram, electroencephalogram, electromyogram, body fat, and heart rate are monitored in contemporary commercialized wearable devices [6–8]. Such battery-operated wearable systems inherently require low power, and, thereby, an ultra-low-power health monitoring circuit. An instrumentation amplifier (IA) is one of the most important building blocks for biopotential signal acquisition. High signal-to-noise ratio at the amplifier output is required for further processing in subsequent stages. Generally, a low-noise design requires higher power consumption, because the input-referred noise can be lowered by increasing the power consumption. In biopotential applications, reducing the flicker noise is an important issue because the flicker noise (1/f noise) is dominant in the low-frequency band. The dominant factors of flicker noise are fluctuations in carrier number and mobility due to the traps at the interface of the silicon and gate oxide [9]. Many research studies have reported a reduction in the flicker noise by various techniques, including correlated double sampling [10], chopper stabilization [11–14], large signal excitation [15,16], and bulk switching scheme [17]. In this paper, we present a dynamic IA scheme to reduce power consumption in an analog readout channel using power gating (PG). In addition, to recover worsened noise level according to the dynamic IA adaptation, chopper-stabilization (CS), and alternating input switching (AIS) techniques are investigated. The IA is designed to be fully reconfigurable, and can be operated in various combinations with power gating, chopper stabilization, and alternating input switching. In this paper, the optimal combination and operating conditions between PG, CS, and AIS are also investigated.

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2. Circuit Design 2. Circuit Design 2.1. Top Level Architecture 2.1. Top Level Architecture Figure 1 shows the block diagram of the biopotential readout channel with the dynamic IA. The Figure 1 shows the signal block diagram of the by biopotential readout channel withThe the dynamic The electrocardiogram (ECG) is modulated the chopping clock, “clk_in”. chopper IA. operation electrocardiogram (ECG) signal is modulated by the chopping clock, “clk_in”. The chopper operation is controlled by programming the chopping clock. The modulated inputs, “IA_ip” and “IA_in”, are is controlled by programming the chopping clock. The modulated inputs, “IA_ip” and “IA_in”, are amplified by the dynamic IA. The dynamic IA consists of a transconductance (TC) input stage and amplified by the dynamic IA. The dynamic IA consists of a transconductance (TC) input stage and transimpedance (TI) output stage. The amplified ECG signal is sampled and held in the “S and H” transimpedance (TI) output stage. The amplified ECG signal is sampled and held in the “S and H” stage. An additional amplification is performed by the programmable gain amplifier (PGA). Finally, stage. An additional amplification is performed by the programmable gain amplifier (PGA). Finally, the high-frequency noise in the amplified ECG signal is removed by the low-pass filter (LPF). The the high-frequency noise in the amplified ECG signal is removed by the low-pass filter (LPF). The readout channel is is designed The operation operationmode modeofofeach eachsub-block sub-block can readout channel designedtotobe befully fullyreconfigurable. reconfigurable. The can be be controlled byby the control can generate generatethe thefully fullyprogrammable programmable clocks controlled the controlregisters. registers.The Theclock clock generator generator can clocks using 32-bit bitstream registers. The internal registers can be accessed via the serial peripheral interface using 32-bit bitstream registers. The internal registers can be accessed via the serial peripheral (SPI). The clock examples the biopotential readout channel are channel shown in The interface (SPI).timing The clock timingfor examples for the biopotential readout areFigure shown2. in biopotential readout channelreadout can be channel configured operating mode for lowmode powerfor and low Figure 2. The biopotential can in be various configured in various operating low noise applications. The applications. PG and the appropriate operations are controlled programming power and low noise The PG andsampling the appropriate sampling operationsby are controlled “clk_dyna” and “clk_SH”. The and AIS “clk_SH”. mode is controlled by programming “clk_DI”. by programming “clk_dyna” The AIS mode is controlled by programming “clk_DI”. Biopotential Read-out Channel with Dynamic IA ECG ECG

clk_in Vip Vip

clk_dyna clk_DI

IA_ip IA_ip

IA_in IA_in

clk_SH

IA_op IA_op

TC_on TC_on

PGA_ip PGA_ip

TI TI stage stage

TC TC stage stage Vin Vin

clk_dyna clk_TI

IA_on IA_on

TC_op TC_op

Dynamic IA PGA_ip PGA_ip

PGA

Vo_PGA Vo_PGA

PGA_in PGA_in

S&H LPF

VO_ana VO_ana

PGA_in PGA_in

Clock generator

Bias generator

Control logic & SPI

Figure1.1.Block Block diagram diagram of of the Figure the biopotential biopotentialreadout readoutchannel. channel. 500 μs μs (2 (2 kHz) kHz) 500

clk_in clk_in 250 μs μs (4 (4 kHz) kHz) 250

clk_DI clk_DI 500 μs μs (2 (2 kHz) kHz) 500

clk_TI clk_TI 250 μs μs (4 (4 kHz) kHz) 250

clk_dyna clk_dyna 62.5 μs μs 62.5

clk_SH clk_SH

Figure for the the biopotential biopotentialreadout readoutchannel. channel. Figure2.2.Clock Clocktiming timing examples examples for

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2.2. Dynamic IA 2.2. Dynamic IA The schematic of the TC input stage, which converts the input differential voltage to output differential current, of is the shown in Figure 3a.which The input transistors are differential operated in voltage a weak to inversion The schematic TC input stage, converts the input output region for achieving transconductance (gm ) efficiency. In DC the V GS (=VGB) differential current, ishigher shown in Figure 3a. The input transistors areoperating operatedpoints, in a weak inversion and VTHfor ofachieving the input higher transistors are 255 mV and 329 mV, respectively. The dynamic IAthe is powered on) region transconductance (gm ) efficiency. In DC operating points, VGS (=VGB and V off control clock signal “clk_dyna”. themV, control clock signal ofisa powered low logic and ofathe input transistors are 255 mV When and 329 respectively. The“clk_dyna” dynamic IA THby level is supplied to the power gating“clk_dyna”. transistors inWhen the TC stage, the clock TC stage will“clk_dyna” be poweredofoff and on and off by a control clock signal the control signal a low vice versa. According to the duty ratio of the control clock “clk_dyna”, the time-averaged power logic level is supplied to the power gating transistors in the TC stage, the TC stage will be powered off consumption of the dynamic IA isratio reduced The inputthe stage transistors power using and vice versa. According to the duty of the proportionally. control clock “clk_dyna”, time-averaged alternating input switching scheme are composed ofThe twoinput MOSstage and transistors two analogusing MUX,alternating as shown consumption of the dynamic(AIS) IA is reduced proportionally. in Figure 3b. With thescheme controlare signal “clk_DI”, either or MOS “IM2” is activated. input switching (AIS) composed of two MOSMOS and “IM1” two analog MUX, as shown in FigureThis 3b. type the of technique with“clk_DI”, alternating input known be helpful reducingThis low-frequency band With control signal either MOSis“IM1” orto MOS “IM2” isinactivated. type of technique noisealternating [16,18]. input is known to be helpful in reducing low-frequency band noise [16,18]. with

VDD

clk_dyna

VDD

Power gating Tr. TC_on

TC_op Input Tr.

Input Tr. Ri

IA_ip

IA_in

clk_DI bias

VSS

VSS (a)

VS clk_DI clk_DI VG

VDD

0 1

0 IM2

IM1

Analog MUX1

VG

1 VDD Analog MUX2

VD (b) Figure 3. (TC) input stage of dynamic IA. (a) of TC input (b) Figure 3. Transconductance Transconductance (TC) input stage of dynamic IA.Schematic (a) Schematic of TCstage; inputand stage; input transistor with alternating input switching (AIS). and (b) input transistor with alternating input switching (AIS).

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The schematic schematic of of the the TI TI output output stage stage is is shown shown in in Figure Figure 4. 4. In currents The In this this stage, stage, the the differential differential currents from TC stage is converted to output voltages using the resistors, Ro. The resistors, Ro, are also used from TC stage is converted to output voltages using the resistors, Ro. The resistors, Ro, are also used as resistive resistive common common mode mode feedback. feedback. The The power power gating gating is is also also applied applied in in the the TI TI stage. stage. When as When the the power power gating clock “clk_dyna” is high, the gate bias voltage is applied, and the TI stage is turned on. When When gating clock “clk_dyna” is high, the gate bias voltage is applied, and the TI stage is turned on. “clk_dyna” is low, the gate bias voltages of PMOS and NMOS become VDD and VSS, respectively; “clk_dyna” is low, the gate bias voltages of PMOS and NMOS become VDD and VSS, respectively; thus, the the TI TI stage stage is is turned turned off. off. thus,

VDD

VDD TC_op

TC_on

clk_dyna

clk_TI

0 Ro IA_on

1

Ro

VDD

bias1

IA_op 0

VSS

1 bias2 clk_TI

clk_dyna

Figure 4. Transimpedance (TI) output stage of dynamic IA.

The input impedance is mainly affected by input capacitance, input leakage current, and The input impedance is mainly affected by input capacitance, input leakage current, and switching switching frequency of CS or AIS. When the switching frequency of 4 kHz, the simulated input frequency of CS or AIS. When the switching frequency of 4 kHz, the simulated input impedance of impedance of this circuit in ECG bandwidth is 415 MΩ. The input impedance of 415 MΩ is much this circuit in ECG bandwidth is 415 MΩ. The input impedance of 415 MΩ is much larger than the larger than the typical impedance of 51 kΩ//47 nF in Ag/AgCl wet electrodes. typical impedance of 51 kΩ//47 nF in Ag/AgCl wet electrodes. 3. Experimental 3. ExperimentalResults Results Figure 55 shows m CMOS Figure shows the the micrograph micrograph of of the the fabricated fabricated readout readout circuit circuit in in the the 0.13-µ 0.13-µm CMOS technology. technology. The chip size is 1.4 mm by 4.3 mm. The supply voltage is 1.2 V, and the supply current without PG PG The chip size is 1.4 mm by 4.3 mm. The supply voltage is 1.2 V, and the supply current without is 10 10 µA. µ A. is The noise spectrum spectrum is The noise is measured measured using using aa spectrum spectrum analyzer, analyzer, 35670A 35670A by by Keysight Keysight Technologies, Technologies, Inc. (Santa Rosa, California, USA), and the input-referred noise is calculated and plotted according Inc. (Santa Rosa, CA, USA), and the input-referred noise is calculated and plotted according to the to the various operation conditions in Figure 6. Theconfigurations clock configurations for operation conditions are various operation conditions in Figure 6. The clock for operation conditions are shown shown in Table 1. The bandwidth of the IA is limited by the fourth-order Bessel low pass filter with in Table 1. The bandwidth of the IA is limited by the fourth-order Bessel low pass filter with 100 Hz 100 Hz frequency. cut-off frequency. The bandwidth of the can be digitally reconfigurable HzHz. to cut-off The bandwidth of the filter canfilter be digitally reconfigurable from 50from Hz to50400 400 Hz. the clocks controlofclocks of “clk_dyna = L”, “clk_LSE = H”, “clk_in = H”,“clk_TI and “clk_TI H”, With theWith control “clk_dyna = L”, “clk_LSE = H”, “clk_in = H”, and = H”, =the IAthe is IA is operated in a static condition and the input-referred noise level is 4.7 μVrms marked as “none” operated in a static condition and the input-referred noise level is 4.7 µVrms marked as “none” in in Figure the static mode withthe thecondition conditionofofalways always“clk_dyna “clk_dyna==L”, L”, the the conventional conventional chopping chopping Figure 6. 6. InIn the static mode with technique and the alternating input switching (AIS) technique are helpful in reducing the noise level.

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technique the alternating input switching (AIS) technique are helpful in reducing the noise 5level. Sensors 2016, and 16, 354 of 10 To reduce the power consumption, the power gating (PG) technique is applied with a clock signal To reduce the power consumption, the power gating (PG) technique is applied with a clock signal having ratio 50% signal “clk_dyna”. The PG PG is technique reduces the power To reduce the power the power gating (PG) technique applied with a clock signal having aa duty duty ratio of ofconsumption, 50% to to the the control control signal “clk_dyna”. The technique reduces the power consumption proportionally to duty ratio of the power gating control signal; however, it increases having a duty ratio of 50% to the control signal “clk_dyna”. The PG technique reduces the power consumption proportionally to the duty ratio of the power gating control signal; however, it increases the noise by The noise level ofpower the dynamic dynamic IA is investigated investigated with the the chopper consumption to theThe duty ratiolevel of the gating IA control signal; however, it increases the noise level levelproportionally by almost almost double. double. noise of the is with chopper stabilization (CS) AIS techniques. the noise level by and almost The noise level of the dynamic IA is investigated with the chopper stabilization (CS) and AISdouble. techniques. stabilization (CS) and AIS techniques.

Readout channel Readout channel

BIAS BIAS 4.3 mm 4.3 mm

Figure channel with with the the dynamic dynamic IA. IA. Figure 5. 5. Chip Chip micrograph micrograph of of the the biopotential biopotential readout readout channel Figure 5. Chip micrograph of the biopotential readout channel with the dynamic IA.

[μVrms] level Noise [μVrms] level Noise

10.0 10.0

PG 4 kHz + AIS PG 4 kHz + AIS PG only PG only AIS only AIS only CS only CS only PG 4 kHz + CS PG 4 kHz + CS none none

1.0 1.0

0.1 0.1 0 0

5 10 5 Switching frequency10[kHz] Switching frequency [kHz]

15 15

Figure 6. Input-referred noise level according to various operation conditions. Figure 6. 6. Input-referred Input-referred noise noise level level according Figure according to to various various operation operation conditions. conditions.

clk_in clk_in clk_in clk_DI clk_DI clk_DI clk_TI clk_TI clk_TI clk_dyna clk_dyna clk_dyna

clk_SH clk_SH clk_SH

Table 1. Clock configurations for various operation conditions. Table 1. Table 1. Clock Clock configurations configurations for for various various operation operation conditions. conditions. PG 4 kHz + AIS PG only AIS only CS only PG PG AISonly only CSonly only Chopper freq. PG4 4kHz kHz++AIS AIS PG only only AIS CS Static “H” Static “H” Static “H” Chopper freq. clock Chopper freq. Static “H” Static “H” Static “H” Static “H” Static “H” Static “H” clock AIS freq. clock Static “H” AIS freq. clock Static clock “H” AIS freq. clock Static “H” AIS freq. clock Static “H” Chopper AIS freq. clock Static “H” AIS freq. clock Static “H”freq. Static “H” Static “H” Static “H” Chopper freq. clock Static “H” Static “H” Static “H” Chopper freq. Static “H” Static “H” Static “H” clock 4 kHz clock PG freq. clock Static “H” Static clock “H” kHz clock clock PG freq. freq. clock clock Static “H” Static “H” 44 kHz PG 4 kHz clock PG freq. clock Static “H” Static “H” 4 kHz PG with 1/4clock duty withfreq. 1/4 clock duty Static “H” Static “H” 4 kHz clock with PG freq. clock Static Static withratio 1/4 duty withratio 1/4 duty Static“H” “H” Static“H” “H” 1/4 duty ratio with 1/4 duty ratio ratio ratio

PG 4 kHz + CS PG kHz+freq. +CS CS Chopper PG 44kHz

Chopper clockfreq. Static “H” Static “H” Chopper freq. Static “H” Chopper clockfreq. Chopper freq. clock clock Static “H” Static “H” 4Static kHz “H” clock 4 kHz clock with 1/4 duty 4 kHz clock with withratio 1/4 duty 1/4 duty ratio ratio

Chopper freq. clock clock

The performance comparisons including noise efficiency factor (NEF) between The performance including noise are efficiency factor (NEF) operating conditions atcomparisons 2 kHz switching frequency also summarized in between Table 2. operating conditions at 2 kHz switching frequency are also summarized in Table 2. calculated as Equation (1): calculated as Equation (1):

2 I tot NEF  Vni ,rms 2 I tot  BW NEF  Vni ,rms πUT  4kT πUT  4kT  BW

the various the various The NEF is The NEF is

(1) (1)

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The performance comparisons including noise efficiency factor (NEF) between the various operating conditions at 2 kHz switching frequency are also summarized in Table 2. The NEF is calculated as Equation (1): d 2Itot 6 of(1) 10 πUT ¨ 4kT ¨ BW where Vni,rms isisthe UT refers to the where V theinput inputreferred referrednoise, noise,BW BWisisthe the3-dB 3-dB bandwidth bandwidth of of the the amplifier, amplifier, U T refers to the ni,rms thermal voltage, and I tot is the supply current of the amplifier. thermal voltage, and I is the supply current of the amplifier. Sensors 2016, 16, 354

NEF “ Vni,rms

tot

Table Table 2. 2. Comparison Comparison of of operation operation conditions conditions at at 22 kHz kHz switching switching frequency. frequency.

PG 4 kHz + PG only 4 kHz + AIS2 kHz PG only AIS 2PG kHz 2 kHz 2 kHz Input noise (μVrms) 3.4 9.1 Input noise (µVrms) 3.4 Supply current (μA) 5 5 9.1 Supply current (µA) 5 5 Bandwidth (Hz) (Hz) 100 100 100 Bandwidth 100 NEF NEF 29.8 29.8 79.9 79.9

AIS only AIS only 2 kHz 2 kHz

2.4

2.4 10 10 100 100 29.8 29.8

CS only PG 4 kHz + PG 4 kHz + CS kHz CS 2 kHz 2 kHz 0.69 0.92 0.69 0.92 10 5 10 5 100 100 100 100 8.6 7.9 8.6 7.9

CS only2 2 kHz

The lowest Vrms is measured at the chopper frequency of 2 kHz, wherein lowest noise noise level level of of 0.69 0.69 µµVrms the input-referred noise is measured Vrms with PG only. At the same chopper frequency input-referred noise is measured to to be be 9.1 9.1 µµVrms frequency of 2 kHz, the input-referred noise is reduced to be 3.4 µVrms µ Vrmswith withthe thecombination combinationof ofPG PGand andAIS. AIS. The most helpful technique in the dynamic IA is the combination of the PG and CS method. The most helpful technique in the dynamic IA is the combination of the PG and CS method. input referred noisenoise and NEF withwith the combination of PGof4PG kHz and CS kHz are 0.92 Vrms and The input referred and NEF the combination 4 kHz and2 CS 2 kHz are µ0.92 µVrms 7.9, In terms of the power consumption, PGPG with the and respectively. 7.9, respectively. In terms of the power consumption, with thehalf halfduty dutycycle cycleisis equivalent equivalent to reducing the bias current to one half. When the bias current is reduced to one half, the thermal noise component, which whichisisdominant dominantinin chopper stabilized amplifier, increase approximately by a chopper stabilized amplifier, will will increase approximately by a factor ‘ factor thisthe case, thereferred input referred noise CS with half bias current istoexpected to be of 2. of In √2. thisIn case, input noise with CS with half bias current is expected be 0.97 µVrms ‘ 0.97 (=√2 ∙ 0.69 The combination PG and CS NEF shows better NEF andreferred lower input (= 2μVrms ¨ 0.69 µVrms). TheμVrms). combination of PG and CSofshows better and lower input noise referred noise level thanvalues the expected values CScurrent. and half bias current. level than the expected of CS and half of bias Figure 7 shows noise spectrum spectrum examples examples in in cases cases of of power power gating gating with with aa 4 kHz clock and a combination of ofpower powergating gating with 4 kHz and chopping Bythe adding the technique, chopping with 4 kHz and chopping with 2 with kHz. 2BykHz. adding chopping technique, the low-frequency noise gating in thetechnique power is gating technique is reduced. noise The the low-frequency band noise inband the power reduced. The input-referred input-referred noise is reduced to 0.92 µ Vrms with the combination of PG and CS. By applying is reduced to 0.92 µVrms with the combination of PG and CS. By applying the half duty-cycled the PG half and CS,ofa50% power reduction µ A reduction to 5 µ A, and a noise reduction of and duty-cycled CS, a power PG reduction from 10 µA toof550% µA, from and a10 noise of 90% from 9.1 µVrms 90% from 9.1 µcan Vrms 0.92 µ Vrms can be achieved. to 0.92 µVrms be to achieved.

Noise density [μVrms/rt Hz]

1.E-03

PG 4kHz + CS 2kHz

PG 4kHz 1.E-04

1.E-05

1.E-06 0.1

1

10 Frequency [Hz]

100

Input-referred noise spectrum of PG 4 kHz and PG 4 kHz + CS 2 kHz. Figure 7. Input-referred

The measured frequency responses including gain and phase plot are shown in Figure 8. The phase distortions are important parameter for high quality ECG recording [19,20]. Although the post-processed digital filter can be used for reducing the phase distortions, the analog filters with inherent phase distortions are used in this system to achieve low power, small size, and real-time signal acquisition, which are important in wearable devices.

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The measured frequency responses including gain and phase plot are shown in Figure 8. The phase distortions are important parameter for high quality ECG recording [19,20]. Although the post-processed digital filter can be used for reducing the phase distortions, the analog filters with inherent phase distortions are used in this system to achieve low power, small size, and real-time Sensors 2016, 16, 354 7 of 10 Sensors 2016, 16,which 354 7 of 10 signal acquisition, are important in wearable devices.

Gain (dB)

Gain (dB)

50 50 40 40

30 30 20 20 10 10 0

100 100

0

-50

Phase (deg)

Phase (deg)

-50

-100

-100

-150

-150

-200

-200 -250

-250 -300

-300

100

10

100

10

Frequency (Hz)

Frequency (Hz) Figure 8. 8.Measured response. Figure Measured frequency frequency response. Figure 8. Measured frequency response. In the time domain, the measured waveform using ECG simulator is shown in Figure 9a. The In measured the time ECG domain, the measured waveform usingshown ECG in simulator is shown in wet Figure 9a. waveforms for 8 h with wet electrodes Figure 9b. The In the time domain, the measured waveform using are ECG simulator is shown in Ag/AgCl Figure 9a. The The measured ECG waveforms forh8with hare with wet are shown in Figure The Ag/AgCl electrodes of waveforms 3M™ Red Dot™ used for electrodes ECG signal acquisition. The gainThe of9b. the readout measured ECG for 8 [21] wet electrodes are shown in Figure 9b. Ag/AgCl wet wet electrodes ofset 3M™ Red Dot™ [21]are areused used ECG signal The ofreadout the readout channel of is to 171 V/V. The input ECG signal is ECG preserved with aacquisition. 50% power electrodes 3M™ Red Dot™ [21] forfor signal acquisition. Thereduction gain gain of compared the toisthe static condition and 90% noise reduction to the power condition. The transient channel setis to V/V. The input ECG signal is preserved preserved with agating 50% power reduction compared channel set171 to 171 V/V. The input ECG signalcompared is with a 50% power reduction compared switching noises due to the switching operations in PG and CS are removed by the fourth-order to thetostatic condition and 90% noise thepower power gating condition. The transient the static condition and 90% noisereduction reduction compared compared totothe gating condition. The transient 100 Hz low pass filter. For example, the 2 kHz switching noises are attenuated by −104 dB

switching noises switchingoperations operations in removed by the fourth-order switching noises duedue to to thetheswitching inPG PGand andCSCSareare removed by the fourth-order (=−80 dB/dec ∙ log(2 kHz/100 Hz) dec).the The2bandwidth of the filter canare be digitally reconfigurable 100 Hz low pass filter. For example, kHz switching noises attenuated by −104 dB dB 100 Hz low pass filter. For example, the 2 kHz switching noises are attenuated by ´104 from 50 Hz to 400 Hz. Power Gating 4kHz + Chop 2kHz (=−80 dB/dec ∙ log(2 kHz/100Hz) Hz)dec). dec). The The bandwidth filter cancan be be digitally reconfigurable (=´80 dB/dec ¨ log(2 kHz/100 bandwidthofofthe the filter digitally reconfigurable 50to Hz400 to 400 Hz. fromfrom 50 Hz Hz.0.8

Power Gating 4kHz + Chop 2kHz

0.7

Voltage (V)[V] Amplitude

Voltage (V)[V] Amplitude

0.8

0.6

0.7

0.5

0.6

0.4

0.50.3 0.40.2 0.30.1 0.2 0 0 0.1

1

2

3

4

5

(s) TimeTime [sec]

0 0

1

2 (a)

3

(s) TimeTime [sec] (a)

Figure 9. Cont.

4

5

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(b)

(b)

Figure 9. Measured ECG signals in the time domain. (a) Measured waveform using ECG simulator;

Figure 9. 9. Measured ECG ECG signals in in the time time domain. domain. (a) (a) Measured Measured waveform waveform using using ECG ECG simulator; simulator; Figure and Measured (b) measured ECGsignals signals forthe eight hours with wet electrodes. and (b) measured ECG signals for eight hours with wet electrodes. and (b) measured ECG signals for eight hours with wet electrodes. The measured common mode rejection ratio (CMRR) is shown in Figure 10. At 60 Hz, the differential mode gain and mode the common mode gain(CMRR) are measured to be 44.7 dB and10. −46.6 The measured common rejection ratio is shown in Figure At 60 Hz, The measured common mode rejection ratio (CMRR) AtdB; 60thus, Hz, the the the CMRR is calculated to 91.3 dB. differential mode gain and the common mode gain are measured to be 44.7 dB and −46.6 dB; thus, differential mode gain and the common mode gain are measured to be 44.7 dB and ´46.6 dB; thus, the

the CMRR is calculated to 91.3 CMRR is calculated to 91.3 dB. dB. 60.0

Differential mode gain

44.7 dB @ 60 Hz

60.0 40.0

Differential mode gain

40.0 20.0 Gain (dB)

Gain (dB)

20.0

CMRR = 91.3 dB @ 60 Hz

0.0

-20.0

0.0

-40.0

CMRR = 91.3 dB @ 60 Hz

Common mode gain

-20.0

-46.6 dB @ 60 Hz

-60.0

-40.0

44.7 dB @ 60 Hz

Common mode gain

-80.0 -46.6 dB @ 60 Hz

-60.0

-100.0 10

-80.0

-100.0 10

100 Frequency (Hz)

Figure 10. Measured CMRR. 100 Frequency (Hz)

Figure 10. 10. Measured Measured CMRR. CMRR. Figure

1,000

1,000

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4. Conclusions A low-noise and low-power dynamic IA scheme was presented. A dynamic IA that can reduce power consumption with a timely piecewise power-gating method and noise level with an alternating input and chopper stabilization technique is fabricated with a 0.13-µm CMOS. The combination of power gating and chopper stabilization results in a lower noise performance than the combination of power gating and alternating input switching scheme. With the combination of power gating and chopper stabilization, the supply current is reduced from 10 µA to 5 µA, and the input-referred noise is reduced from 9.1 µVrms to 0.92 µVrms. The power consumption and noise level of the fabricated chip are summarized and compared with the recently-published results summarized in Table 3. In our proposed architecture, we have shown that the dynamic IA technique can achieve a 50% reduction in power consumption and recover the signal-quality deterioration by 90%. Table 3. IA performance summary and comparison with previous works. This Work

[22]

[23]

[24]

Technology

130 nm

180 nm

65 nm

180 nm

Supply

1.2 V

1.2 V

1V

1V

IA current

10 µA (static mode) 5 µA (half duty-cycled power gating mode)

5 µA

1.8 µA

3.5 µA

Input-referred noise (~100 Hz)

0.6 µVrms (static mode) 0.9 µVrms (half duty-cycled power gating mode)

1.3 µVrms

6.7 µVrms

1.3 µVrms

Input impedance

415 MΩ (simulated)

1 GΩ

N/A

700 MΩ

CMRR

91.3 dB

120 dB

134 dB

60 dB

Acknowledgments: This work was supported by Chungnam National University. Author Contributions: Jongpal Kim is the first author, and he drafted the manuscript. He also implemented the circuit blocks and designed the top architecture of the IC. Hyoungho Ko is the corresponding author, and he designed the analog blocks of the IC. Conflicts of Interest: The authors declare no conflict of interest.

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