19-2983; Rev 3; 1/10

KIT ATION EVALU E L B AVAILA

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Features

The MAX5590–MAX5595 octal, 12/10/8-bit, voltage-output digital-to-analog converters (DACs) offer buffered outputs and a 3µs maximum settling time at the 12-bit level. The DACs operate from a +2.7V to +5.25V analog supply and a separate +1.8V to +5.25V digital supply. The 20MHz 3-wire serial interface is compatible with SPI™, QSPI™, MICROWIRE™, and digital signal processor (DSP) protocol applications. Multiple devices can share a common serial interface in direct-access or daisy-chained configuration. The MAX5590–MAX5595 provide two multifunction, user-programmable, digital I/O ports. The externally selectable power-up states of the DAC outputs are either zero scale, midscale, or full scale. Software-selectable FAST and SLOW settling modes decrease settling time in FAST mode, or reduce supply current in SLOW mode. The MAX5590/MAX5591 are 12-bit DACs, the MAX5592/ MAX5593 are 10-bit DACs, and the MAX5594/ MAX5595 are 8-bit DACs. The MAX5590/MAX5592/ MAX5594 provide unity-gain-configured output buffers, while the MAX5591/MAX5593/MAX5595 provide forcesense-configured output buffers. The MAX5590– MAX5595 are specified over the extended -40°C to +85°C temperature range, and are available in spacesaving 24-pin and 28-pin TSSOP packages.

o Octal, 12/10/8-Bit Serial DACs in TSSOP Packages

Applications

Ordering Information

Portable Instrumentation Automatic Test Equipment (ATE) Digital Offset and Gain Adjustment Automatic Tuning Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Controls Motion Control Microprocessor (µP)-Controlled Systems Power Amplifier Control Fast Parallel-DAC to Serial-DAC Upgrades

o 3µs (max) 12-Bit Settling Time to 1/2 LSB o Integral Nonlinearity: 1 LSB (max) MAX5590/MAX5591 A-Grade (12-Bit) 1 LSB (max) MAX5592/MAX5593 (10-Bit) 1/2 LSB (max) MAX5594/MAX5595 (8-Bit) o Guaranteed Monotonic, ±1 LSB (max) DNL o Two User-Programmable Digital I/O Ports o Single +2.7V to +5.25V Analog Supply o +1.8V to AVDD Digital Supply o 20MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-/DSPCompatible Serial Interface o Glitch-Free Outputs Power Up to Zero Scale, Midscale, or Full Scale Controlled by PU Pin o Unity-Gain or Force-Sense-Configured Output Buffers

PART

TEMP RANGE

PIN-PACKAGE

MAX5590AEUG+*

-40°C to +85°C

24 TSSOP

MAX5590BEUG+

-40°C to +85°C

24 TSSOP

MAX5591AEUI+*

-40°C to +85°C

28 TSSOP

MAX5591BEUI+

-40°C to +85°C

28 TSSOP

MAX5592EUG+

-40°C to +85°C

24 TSSOP

MAX5593EUI+

-40°C to +85°C

28 TSSOP

MAX5594EUG+

-40°C to +85°C

24 TSSOP

MAX5595EUI+

-40°C to +85°C

28 TSSOP

*Future product—contact factory for availability. Specifications are preliminary.

+Denotes a lead(Pb)-free/RoHS-compliant package.

Selector Guide and Pin Configurations appear at end of data sheet. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.

1

MAX5590–MAX5595

General Description

MAX5590–MAX5595

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS AVDD to DVDD ........................................................................±6V AGND to DGND ..................................................................±0.3V AVDD to AGND, DGND.............................................-0.3V to +6V DVDD to AGND, DGND ............................................-0.3V to +6V FB_, OUT_, REF to AGND ........-0.3V to the lower of (AVDD + 0.3V) or +6V SCLK, DIN, CS, PU, DSP to DGND .......-0.3V to the lower of (DVDD + 0.3V) or +6V UPIO1, UPIO2 to DGND ...............-0.3V to the lower of (DVDD + 0.3V) or +6V

Maximum Current into Any Pin .........................................±50mA Continuous Power Dissipation (TA = +70°C) 24-Pin TSSOP (derate 13.9mW/°C above +70°C) .....1111mW 28-Pin TSSOP (derate 14mW/°C above +70°C) ........1117mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, VAGND = 0V, VDGND = 0V, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC ACCURACY Resolution

N

MAX5590/MAX5591

12

MAX5592/MAX5593

10

MAX5594/MAX5595

Integral Nonlinearity

Differential Nonlinearity

Offset Error

INL

DNL

VOS

VREF = 2.5V at AVDD = 2.7V and VREF = 4.096V at AVDD = 5.25V (Note 2)

Bits

8 MAX5590A/MAX5591A (12-bit) MAX5590B/MAX5591B (12-bit)

±1 ±2

±4

MAX5592/MAX5593 (10-bit)

±0.5

±1

MAX5594/MAX5595 (8-bit)

±0.125

±0.5

LSB

Guaranteed monotonic (Note 2)

±1

MAX5590A/MAX5591A (12-bit), decimal code = 40

±5

MAX5590B/MAX5591B (12-bit), decimal code = 40

±5

±25

MAX5592/MAX5593 (10-bit), decimal code = 10

±5

±25

MAX5594/MAX5595 (8-bit), decimal code = 3

±5

±25

Offset-Error Drift

Gain Error

Gain-Error Drift

2

GE

Full-scale output

mV

ppm of FS/°C

5 MAX5590A/MAX5591A (12-bit)

LSB

±4

MAX5590B/MAX5590B (12-bit)

±20

±40

MAX5592/MAX5593 (10-bit)

±5

±10

MAX5594/MAX5595 (8-bit)

±2

±3

1

_______________________________________________________________________________________

LSB

ppm of FS/°C

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, VAGND = 0V, VDGND = 0V, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER

SYMBOL

Power-Supply Rejection Ratio

PSRR

CONDITIONS

MIN

Full-scale output, AVDD = 2.7V to 5.25V

TYP

MAX

200

UNITS µV/V

REFERENCE INPUT Reference Input Range

VREF

Reference Input Resistance

RREF

Reference Leakage Current

0.25 Normal operation (no code dependence)

145

Shutdown mode

AVDD 200 0.5

V kΩ

1

µA

DAC OUTPUT CHARACTERISTICS SLOW mode, full scale Output Voltage Noise FAST mode, full scale Output Voltage Range (Note 3)

Unity gain

85

Force sense

67

Unity gain

140

Force sense

µVRMS

110

Unity-gain output

0

AVDD

Force-sense output

0

AVDD / 2

DC Output Impedance

Ω

38

Short-Circuit Current

AVDD = 5V, OUT_ to AGND, full scale, FAST mode

57

AVDD = 3V, OUT_ to AGND, full scale, FAST mode

45

V

mA

Power-Up Time

From VDD applied until interface is functional

30

Wake-Up Time

Coming out of shutdown, outputs settled

40

60

µs

µs

Output OUT_ and FB_ Open-Circuit Leakage Current

Programmed in shutdown mode, force-sense outputs only

0.01

µA

DIGITAL OUTPUTS (UPIO_) Output High Voltage

VOH

ISOURCE = 2mA

Output Low Voltage

VOL

ISINK = 2mA

DVDD 0.5

V 0.4

V

DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_) Input High Voltage

VIH

DVDD ≥ 2.7V

2.4

DVDD < 2.7V

0.7 x DVDD

V

DVDD > 3.6V Input Low Voltage

VIL

0.8

2.7V ≤ DVDD ≤ 3.6V

0.6

DVDD < 2.7V

0.2

Input Leakage Current

IIN

±0.1

Input Capacitance

CIN

10

±1

V µA pF

_______________________________________________________________________________________

3

MAX5590–MAX5595

ELECTRICAL CHARACTERISTICS (continued)

MAX5590–MAX5595

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, VAGND = 0V, VDGND = 0V, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PU INPUT Input High Voltage

VIH-PU

Input Low Voltage

VIL-PU

Input Leakage Current

IIN-PU

DVDD 200mV

V

PU still considered unconnected when connected to a tri-state bus

200

mV

±200

nA

DYNAMIC PERFORMANCE Voltage-Output Slew Rate

SR

FAST mode

3.6

SLOW mode

1.6

FAST mode

Voltage-Output Settling Time (Note 5)

V/µs

MAX5590/MAX5591 from code 322 to code 4095 to 1/2 LSB

2

3

MAX5592/MAX5593 from code 10 to code 1023 to 1/2 LSB

1.5

3

MAX5594/MAX5595 from code 3 to code 255 to 1/2 LSB

1

2 µs

SLOW mode

MAX5590/MAX5591 from code 322 to code 4095 to 1/2 LSB

3

6

MAX5592/MAX5593 from code 10 to code 1023 1/2 LSB

2.5

6

MAX5594/MAX5595 from code 3 to code 255 to 1/2 LSB

2

4

FB_ Input Voltage

0

FB_ Input Current

VREF / 2

V

0.1

µA

Unity gain

200

Force sense

150

Digital Feedthrough

CS = DVDD, code = zero scale, any digital input from 0 to DVDD and DVDD to 0, f = 100kHz

0.1

nV-s

Digital-to-Analog Glitch Impulse

Major carry transition

2

nV-s

DAC-to-DAC Crosstalk

(Note 4)

15

nV-s

Reference -3dB Bandwidth (Note 6)

4

_______________________________________________________________________________________

kHz

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, VAGND = 0V, VDGND = 0V, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

POWER REQUIREMENTS Analog Supply Voltage Range

AVDD

2.70

5.25

V

Digital Supply Voltage Range

DVDD

1.8

AVDD

V

Operating Supply Current

Shutdown Supply Current

IAVDD + IDVDD

SLOW mode, all digital inputs Unity gain at DGND or DVDD, no load, Force sense VREF = 4.096V

1.5

3.2

2.4

4.8

FAST mode, all digital inputs at DGND or DVDD, no load, VREF = 4.096V

Unity gain

2.5

8

Force sense

3.4

8

0.5

1

IAVDD(SHDN) No clocks, all digital inputs at DGND or DVDD, all + DACs in shutdown mode IDVDD(SHDN)

mA

µA

Note 1: For the force-sense versions, FB_ is connected to its respective OUT_. VOUT (max) = VREF / 2, unless otherwise noted. Note 2: Linearity guaranteed from decimal code 40 to code 4095 for the MAX5590B/MAX5591B (12-bit, B-grade), code 10 to code 1023 for the MAX5592/MAX5593 (10-bit), and code 3 to code 255 for the MAX5594/MAX5595 (8-bit). Note 3: Represents the functional range. The linearity is guaranteed at VREF = 2.5V (for AVDD from 2.7V to 5.25V), and VREF = 4.096V (for AVDD = 4.5V to 5.25V). See the Typical Operating Characteristics section for linearity at other voltages. Note 4: DC crosstalk is measured as follows: outputs of DACA–DACH are set to full scale and the output of DACH is measured. While keeping DACH unchanged, the outputs of DACA–DACG are transitioned to zero scale and the ∆VOUT of DACH is measured. Note 5: Guaranteed by design. Note 6: The reference -3dB bandwidth is measured with a 0.1VP-P sine wave on VREF and with full-scale input code.

_______________________________________________________________________________________

5

MAX5590–MAX5595

ELECTRICAL CHARACTERISTICS (continued)

MAX5590–MAX5595

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1) (DVDD = 2.7V to 5.25V, VAGND = 0V, VDGND = 0V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER

SYMBOL

SCLK Frequency SCLK Pulse-Width High

fSCLK

CONDITIONS

MIN

TYP

2.7V < DVDD < 5.25V

MAX

UNITS

20

MHz

tCH

(Note 7)

20

ns

SCLK Pulse-Width Low

tCL

(Note 7)

20

ns

CS Fall to SCLK Rise Setup Time

tCSS

10

ns

SCLK Rise to CS Rise Hold Time

tCSH

5

ns

SCLK Rise to CS Fall Setup

tCS0

10

ns

DIN to SCLK Rise Setup Time

tDS

12

ns

DIN to SCLK Rise Hold Time

tDH

5

ns

SCLK Rise to DOUTDC1 Valid Propagation Delay

tDO1

CL = 20pF, UPIO_ = DOUTDC1 mode

30

ns

SCLK Fall to DOUT_ Valid Propagation Delay

tDO2

CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB mode

30

ns

CS Rise to SCLK Rise Hold Time

tCS1

MICROWIRE and SPI modes 0 and 3

CS Pulse-Width High

tCSW

10

ns

45

ns

UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes

tDOZ

CL = 20pF, from end of write cycle to UPIO_ in high impedance

100

ns

DOUTRB Tri-State Time from CS Rise

tDRBZ

CL = 20pF, from rising edge of CS to UPIO_ in high impedance

20

ns

DOUTRB Tri-State Enable Time from 8th SCLK Rise

tZEN

CL = 20pF, from 8th rising edge of SCLK to UPIO_ driven out of tri-state

0

ns

LDAC Pulse-Width Low

tLDL

Figure 5

20

ns

LDAC Effective Delay

tLDS

Figure 6

100

ns

CLR, MID, SET Pulse-Width Low

tCMS

Figure 5

20

ns

GPO Output Settling Time

tGP

Figure 6

GPO Output High-Impedance Time

tGPZ

6

_______________________________________________________________________________________

100

ns

100

ns

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs (DVDD = 1.8V to 5.25V, VAGND = 0V, VDGND = 0V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER

SYMBOL

SCLK Frequency

fSCLK

CONDITIONS

MIN

1.8V < DVDD < 5.25V

TYP

MAX

UNITS

10

MHz

SCLK Pulse-Width High

tCH

(Note 7)

40

ns

SCLK Pulse-Width Low

tCL

(Note 7)

40

ns

CS Fall to SCLK Rise Setup Time

tCSS

20

ns

SCLK Rise to CS Rise Hold Time

tCSH

0

ns

SCLK Rise to CS Fall Setup

tCS0

10

ns

DIN to SCLK Rise Setup Time

tDS

20

ns

DIN to SCLK Rise Hold Time

tDH

5

ns

SCLK Rise to DOUTDC1 Valid Propagation Delay

tDO1

CL = 20pF, UPIO_ = DOUTDC1 mode

60

ns

SCLK Fall to DOUT_ Valid Propagation Delay

tDO2

CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB mode

60

ns

CS Rise to SCLK Rise Hold Time

tCS1

MICROWIRE and SPI modes 0 and 3

CS Pulse-Width High

tCSW

20

ns

90

ns

UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes

tDOZ

CL = 20pF, from end of write cycle to UPIO_ in high impedance

200

ns

DOUTRB Tri-State Time from CS Rise

tDRBZ

CL = 20pF, from rising edge of CS to UPIO_ in high impedance

40

ns

DOUTRB Tri-State Enable Time from 8th SCLK Rise

tZEN

CL = 20pF, from 8th rising edge of SCLK to UPIO_ driven out of tri-state

0

ns

LDAC Pulse-Width Low

tLDL

Figure 5

40

ns

LDAC Effective Delay

tLDS

Figure 6

200

ns

CLR, MID, SET Pulse-Width Low

tCMS

Figure 5

40

ns

GPO Output Settling Time

tGP

Figure 6

GPO Output High-Impedance Time

tGPZ

200

ns

200

ns

_______________________________________________________________________________________

7

MAX5590–MAX5595

TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)

MAX5590–MAX5595

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2) (DVDD = 2.7V to 5.25V, VAGND = 0V, VDGND = 0V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER

SYMBOL

SCLK Frequency SCLK Pulse-Width High

fSCLK

CONDITIONS

MIN

TYP

2.7V < DVDD < 5.25V

MAX

UNITS

20

MHz

tCH

(Note 7)

SCLK Pulse-Width Low

tCL

(Note 7)

20

ns

CS Fall to SCLK Fall Setup Time

tCSS

10

ns

DSP Fall to SCLK Fall Setup Time

tDSS

10

ns

SCLK Fall to CS Rise Hold Time

tCSH

5

ns

SCLK Fall to CS Fall Delay

tCS0

10

ns

SCLK Fall to DSP Fall Delay

tDS0

10

ns

DIN to SCLK Fall Setup Time

tDS

12

ns

DIN to SCLK Fall Hold Time

tDH

5

ns

SCLK Rise to DOUT_ Valid Propagation Delay

tDO1

CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB mode

30

ns

SCLK Fall to DOUT_ Valid Propagation Delay

tDO2

CL = 20pF, UPIO_ = DOUTDC0 mode

30

ns

CS Rise to SCLK Fall Hold Time

tCS1

MICROWIRE and SPI modes 0 and 3

10

ns

CS Pulse-Width High

tCSW

45

ns

DSP Pulse-Width High

tDSW

20

ns

DSP Pulse-Width Low

tDSPWL

20

ns

(Note 8)

20

ns

UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes

tDOZ

CL = 20pF, from end of write cycle to UPIO_ in high impedance

100

ns

DOUTRB Tri-State Time from CS Rise

tDRBZ

CL = 20pF, from rising edge of CS to UPIO_ in high impedance

20

ns

DOUTRB Tri-State Enable Time from 8th SCLK Fall

tZEN

CL = 20pF, from 8th falling edge of SCLK to UPIO_ driven out of tri-state

LDAC Pulse-Width Low

tLDL

LDAC Effective Delay

tLDS

CLR, MID, SET Pulse-Width Low

0

ns

Figure 5

20

ns

Figure 6

100

ns

20

tCMS

Figure 5

GPO Output Settling Time

tGP

Figure 6

GPO Output High-Impedance Time

tGPZ

8

_______________________________________________________________________________________

ns 100

ns

100

ns

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs (DVDD = 1.8V to 5.25V, VAGND = 0V, VDGND = 0V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER

SYMBOL

SCLK Frequency

fSCLK

SCLK Pulse-Width High

CONDITIONS

MIN

1.8V < DVDD < 5.25V

TYP

MAX

UNITS

10

MHz

tCH

(Note 7)

SCLK Pulse-Width Low

tCL

(Note 7)

40

ns

CS Fall to SCLK Fall Setup Time

tCSS

20

ns

DSP Fall to SCLK Fall Setup Time

tDSS

20

ns

SCLK Fall to CS Rise Hold Time

tCSH

0

ns

SCLK Fall to CS Fall Delay

tCS0

10

ns

SCLK Fall to DSP Fall Delay

tDS0

15

ns

DIN to SCLK Fall Setup Time

tDS

20

ns

DIN to SCLK Fall Hold Time

tDH

5

ns

SCLK Rise to DOUT_ Valid Propagation Delay

tDO1

CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB mode

60

ns

SCLK Fall to DOUT_ Valid Propagation Delay

tDO2

CL = 20pF, UPIO_ = DOUTDC0 mode

60

ns

CS Rise to SCLK Fall Hold Time

tCS1

MICROWIRE and SPI modes 0 and 3

20

ns

CS Pulse-Width High

tCSW

90

ns

DSP Pulse-Width High

tDSW

40

ns

DSP Pulse-Width Low

tDSPWL

40

ns

(Note 8)

40

ns

UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes

tDOZ

CL = 20pF, from end of write cycle to UPIO_ in high impedance

200

ns

DOUTRB Tri-State Time from CS Rise

tDRBZ

CL = 20pF, from rising edge of CS to UPIO_ in high impedance

40

ns

DOUTRB Tri-State Enable Time from 8th SCLK Fall

tZEN

CL = 20pF, from 8th falling edge of SCLK to UPIO_ driven out of tri-state

LDAC Pulse-Width Low

tLDL

LDAC Effective Delay

tLDS

CLR, MID, SET Pulse-Width Low

0

ns

Figure 5

40

ns

Figure 6

200

ns

40

tCMS

Figure 5

GPO Output Settling Time

tGP

Figure 6

GPO Output High-Impedance Time

tGPZ

ns 200

ns

200

ns

Note 7: In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the following edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns (2.7V) or 50ns (1.8V). Note 8: The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low and CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of operation.

_______________________________________________________________________________________

9

MAX5590–MAX5595

TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2)

Typical Operating Characteristics (AVDD = DVDD = 5V, VREF = 4.096V, RL = 10kΩ, CL = 100pF, speed mode = FAST, PU = unconnected, TA = +25°C, unless otherwise noted.)

3 2

0.50

MAX5590-95 toc02

1.00

MAX5590-95 toc01

4

0.75 0.50

0.25

0

0

-1

-0.25

-2

-0.50

-3

INL (LSB)

0.25

1 INL (LSB)

INL (LSB)

INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (8-BIT)

INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (10-BIT)

MAX5590-95 toc03

INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (12-BIT)

0

-0.25

-0.75 B-GRADE 0

1024

2048

3072

0

256

512

768

1023

-0.50

0

64

128

192

DIGITAL INPUT CODE

DIGITAL INPUT CODE

DIGITAL INPUT CODE

DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (12-BIT)

DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (10-BIT)

DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (8-BIT)

0

-0.25

0.025 DNL (LSB)

0.1 DNL (LSB)

0.25

0.050

0

255

MAX5590-95 toc06

0.2

MAX5590-95 toc04

0.50

DNL (LSB)

-1.00

4095

MAX5590-95 toc05

-4

0

-0.025

-0.1

B-GRADE 0

1024

2048

3072

-0.2

4095

0

256

512

768

1023

-0.050

0

64

128

192

DIGITAL INPUT CODE

DIGITAL INPUT CODE

DIGITAL INPUT CODE

INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE (12-BIT)

DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE (12-BIT)

INTEGRAL NONLINEARITY vs. TEMPERATURE (12-BIT)

3 2

0.4

4

0.3

3 2

0.2

0 -1

0.1

INL (LSB)

DNL (LSB)

1

0 -0.1

255

MAX5590-95 toc09

0.5

MAX5590-95 toc07

4

MAX5590-95 toc08

-0.50

INL (LSB)

MAX5590–MAX5595

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs

1 0 -1

-0.2 -2 -3

B-GRADE MIDSCALE 1.0

1.5

2.0

B-GRADE MIDSCALE

-0.4 -0.5

-4 2.5

3.0 VREF (V)

10

-2

-0.3

3.5

4.0

4.5

5.0

-3

B-GRADE MIDSCALE

-4 1.0

1.5

20

2.5

3.0 VREF (V)

3.5

4.0

4.5

5.0

-40

-15

10

35

TEMPERATURE (°C)

______________________________________________________________________________________

60

85

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs

-0.1

MAX5590-95 toc12

1

12-BIT NO LOAD

12-BIT NO LOAD 0

-15

10

35

60

85

0

1024

2048

3072

0

4095

0

1024

2048

3072

4095

TEMPERATURE (°C)

DIGITAL INPUT CODE

DIGITAL INPUT CODE

SUPPLY CURRENT vs. SUPPLY VOLTAGE (FORCE-SENSE)

SUPPLY CURRENT vs. SUPPLY VOLTAGE (UNITY GAIN)

SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE

2

1

2.0

1.0 0.5

AVDD = DVDD NO LOAD 0

SLOW MODE

1.5

AVDD = DVDD NO LOAD

3.40

4.10

4.80

5.25

2.70

FORCE SENSE 40 UNITY GAIN

30 20 10 NO LOAD

3.40

4.10

4.80

2.70

5.25

3.40

4.10

4.80

5.25

SUPPLY VOLTAGE (V)

SUPPLY VOLTAGE (V)

SUPPLY VOLTAGE (V)

OFFSET ERROR vs. TEMPERATURE

GAIN ERROR vs. TEMPERATURE

OUTPUT VOLTAGE vs. OUTPUT SOURCE/SINK CURRENT

4 FORCE SENSE 3

-4 FORCE SENSE -6 UNITY GAIN

2 UNITY GAIN: 1 LSB = 1mV FORCE SENSE: 1 LSB = 0.5mV -15

10

35

TEMPERATURE (°C)

60

85

MAX5590-95 toc18

1.5

1.0

0

-10

0

MIDSCALE

0.5

-8

UNITY GAIN

1

2.0 OUTPUT VOLTAGE (V)

-2 GAIN ERROR (LSB)

5

2.5

MAX5590-95 toc17

0

MAX5590-95 toc16

CODE = 40 UNITY GAIN: 1 LSB = 1mV FORCE SENSE: 1 LSB = 0.5mV

-40

50

0

0 2.70

MAX5590-95 toc15

60 SHUTDOWN SUPPLY CURRENT (nA)

SLOW MODE

FAST MODE

2.5 SUPPLY CURRENT (mA)

3

MAX5590-95 toc14

3.0

MAX5590-95 toc13

FAST MODE

OFFSET ERROR (LSB)

2

2

1

4

6

3

B-GRADE MIDSCALE -40

7

SUPPLY CURRENT (mA)

0

3

MAX5590-95 toc11

4 SUPPLY CURRENT (mA)

DNL (LSB)

0.1

SUPPLY CURRENT (mA)

5

MAX5590-95 toc10

0.2

-0.2

SUPPLY CURRENT vs. DIGITAL INPUT CODE (UNITY GAIN)

SUPPLY CURRENT vs. DIGITAL INPUT CODE (FORCE-SENSE)

DIFFERENTIAL NONLINEARITY vs. TEMPERATURE (12-BIT)

-40

-15

10

35

TEMPERATURE (°C)

60

85

UNITY GAIN VREF = 4.096V -15

-10

-5

0

5

10

15

IOUT (mA)

______________________________________________________________________________________

11

MAX5590–MAX5595

Typical Operating Characteristics (continued) (AVDD = DVDD = 5V, VREF = 4.096V, RL = 10kΩ, CL = 100pF, speed mode = FAST, PU = unconnected, TA = +25°C, unless otherwise noted.)

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590–MAX5595

Typical Operating Characteristics (continued) (AVDD = DVDD = 5V, VREF = 4.096V, RL = 10kΩ, CL = 100pF, speed mode = FAST, PU = unconnected, TA = +25°C, unless otherwise noted.) MAJOR-CARRY TRANSITION GLITCH

SETTLING TIME NEGATIVE

SETTLING TIME POSITIVE

MAX5590-95 toc19

MAX5590-95 toc21

MAX5590-95 toc20

FULL-SCALE TRANSITION

CS 5V/div CS 5V/div

CS 5V/div

OUT_ 2V/div

OUT_ 2V/div

OUT_ 2mV/div

FULL-SCALE TRANSITION 250ns/div

REFERENCE INPUT BANDWIDTH

GAIN (dB)

-5 -10 -15

VREF = 0.1VP-P AT 4.096VDC UNITY GAIN 1

10

100

DAC-TO-DAC CROSSTALK MAX5590-95 toc24

-40 -50 -60 -70 -80

OUTA–OUTG 2V/div

-90 -100 -110

OUTH 1mV/div

-120 -130

-20 -25

REFERENCE FEEDTHROUGH AT 1kHz MAX5590-95 toc23

0

400ns/div

-22 -30 SIGNAL AMPLITUDE (dB)

MAX5590-95 toc22

5

400ns/div

-142 1000

10,000

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

200µs/div

FREQUENCY (kHz)

FREQUENCY (kHz)

DIGITAL FEEDTHROUGH

EXITING SHUTDOWN TO MIDSCALE

POWER-UP GLITCH

MAX5590-95 toc25

MAX5590-95 toc27

MAX5590-95 toc26

AVDD 2V/div

SCLK 2V/div

CS 2V/div

OUT_ 2V/div

OUT_ (AC-COUPLED) 2mV/div

OUT_ 2V/div PU = DVDD

1µs/div

12

400µs/div

10µs/div

______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs PIN MAX5590 MAX5592 MAX5594

MAX5591 MAX5593 MAX5595

1

1

AVDD

2

2

AGND

Analog Ground

3

3

OUTA

DACA Output

4, 8, 17, 21

—

N.C.

5

6

OUTB

DACB Output

6

7

OUTC

DACC Output

7

10

OUTD

9

11

CS

10

12

SCLK

Serial Clock Input

11

13

DIN

Serial Data Input

12

14

DSP

Clock Enable. Connect DSP to DVDD at power-up to transfer data on the rising edge of SCLK. Connect DSP to GND to transfer data on the falling edge of SCLK. Connect DSP to DGND at power-up to transfer data on the falling edge of SCLK.

NAME

FUNCTION

Analog Supply

No Connection. Not internally connected.

DACD Output Active-Low Chip-Select Input

13

15

DVDD

Digital Supply

14

16

DGND

Digital Ground

15

17

UPIO1

User-Programmable Input/Output 1

16

18

UPIO2

User-Programmable Input/Output 2

18

19

OUTE

DACE Output

19

22

OUTF

DACF Output

20

23

OUTG

DACG Output

22

26

OUTH

DACH Output

23

27

PU

Power-Up State Select Input. Connect PU to DVDD to set OUTA–OUTH to full scale upon power-up. Connect PU to DGND to set OUTA–OUTH to zero upon power-up. Leave PU unconnected at power-up to set OUTA–OUTH to midscale.

24

28

REF

Reference Input

—

4

FBA

Feedback for DACA

—

5

FBB

Feedback for DACB

—

8

FBC

Feedback for DACC

—

9

FBD

Feedback for DACD

—

20

FBE

Feedback for DACE

—

21

FBF

Feedback for DACF

—

24

FBG

Feedback for DACG

—

25

FBH

Feedback for DACH

______________________________________________________________________________________

13

MAX5590–MAX5595

Pin Description

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590–MAX5595

Functional Diagrams

AVDD

CS SCLK DIN

DSP

DVDD

AGND

DGND

SERIAL INTERFACE CONTROL

MAX5590 MAX5592 MAX5594

16-BIT SHIFT REGISTER MUX

UPIO1 UPIO2

PU

UPIO1 AND UPIO2 LOGIC

DOUT REGISTER

POWER-DOWN LOGIC AND REGISTER

DECODE CONTROL

OUTA INPUT REGISTER A

DAC REGISTER A

DACA

INPUT REGISTER H

DAC REGISTER H

DACH

OUTH

REF

14

______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs

AVDD

CS SCLK DIN

DSP

DVDD

AGND

DGND

SERIAL INTERFACE CONTROL

MAX5591 MAX5593 MAX5595

16-BIT SHIFT REGISTER MUX

UPIO1 UPIO2

PU

UPIO1 AND UPIO2 LOGIC

POWER-DOWN LOGIC AND REGISTER

DOUT REGISTER

FBA

DECODE CONTROL

OUTA INPUT REGISTER A

DAC REGISTER A

DACA

FBH

OUTH INPUT REGISTER H

DAC REGISTER H

DACH

REF

______________________________________________________________________________________

15

MAX5590–MAX5595

Functional Diagrams (continued)

MAX5590–MAX5595

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Detailed Description The MAX5590–MAX5595 octal, 12/10/8-bit, voltage-output DACs offer buffered outputs and a 3µs maximum settling time at the 12-bit level. The DACs operate from a single 2.7V to 5.25V analog supply and a separate 1.8V to AVDD digital supply. The MAX5590–MAX5595 include an input register and DAC register for each channel and a 16-bit data-in/data-out shift register. The 3-wire serial interface is compatible with SPI, QSPI, MICROWIRE, and DSP applications. The MAX5590– MAX5595 provide two user-programmable digital I/O ports, which are programmed through the serial interface. The externally selectable power-up states of the DAC outputs are either zero scale, midscale, or full scale.

Reference Input The reference input, REF, accepts both AC and DC values with a voltage range extending from analog ground (AGND) to AVDD. The voltage at REF sets the full-scale output of the DACs. Determine the output voltage using the following equations: Unity-gain versions: VOUT_ = (VREF x CODE) / 2N Force-sense versions (FB_ connected to OUT_): VOUT = 0.5 x (VREF x CODE) / 2N where CODE is the numeric value of the DAC’s binary input code and N is the bits of resolution. For the MAX5590/MAX5591, N = 12 and CODE ranges from 0 to 4095. For the MAX5592/MAX5593, N = 10 and CODE ranges from 0 to 1023. For the MAX5594/ MAX5595, N = 8 and CODE ranges from 0 to 255.

Output Buffers The DACA and DACH output-buffer amplifiers of the MAX5590–MAX5595 are unity-gain stable with rail-torail output voltage swings and a typical slew rate of 3.6V/µs (FAST mode). The MAX5590/MAX5592/ MAX5594 provide unity-gain outputs, while the MAX5591/MAX5593/MAX5595 provide force-sense outputs. For the MAX5591/MAX5593/MAX5595, access to the output amplifier’s inverting input provides flexibility in output gain setting and signal conditioning (see the Applications Information section). The MAX5590–MAX5595 offer FAST and SLOW settlingtime modes. In the SLOW mode, the settling time is 6µs (max), and the supply current is 3.2mA (max). In the FAST mode, the settling time is 3µs (max), and the supply current is 8mA (max). See the Digital Interface section for settling-time mode programming details.

16

Use the serial interface to set the shutdown output impedance of the amplifiers to 1kΩ or 100kΩ for the MAX5590/MAX5592/MAX5594 and 1kΩ or high impedance for the MAX5591/MAX5593/MAX5595. The DAC outputs can drive a 10kΩ (typ) load and are stable with up to 500pF (typ) of capacitive load.

Power-On Reset At power-up, all DAC outputs power up to full scale, midscale, or zero scale, depending on the configuration of the PU input. Connect PU to DVDD to set OUT_ to full scale upon power-up. Connect PU to digital ground (DGND) at power-up to set OUT_ to zero scale. Leave PU unconnected to set OUT_ to midscale.

Digital Interface The MAX5590–MAX5595 use a 3-wire serial interface that is compatible with SPI, QSPI, MICROWIRE, and DSP protocol applications (Figures 1 and 2). Connect DSP to DVDD before power-up to clock data in on the rising edge of SCLK. Connect DSP to DGND before power-up to clock data in on the falling edge of SCLK. After powerup, the device enters DSP frame-sync mode on the first rising edge of DSP. Refer to the MAX5590–MAX5595 Programmer’s Handbook for details. The MAX5590–MAX5595 include a 16-bit input shift register. The data is loaded into the input shift register through the serial interface. The 16 bits can be sent in two serial 8-bit packets or one 16-bit word (CS must remain low until all 16 bits are transferred). The data is loaded MSB first. For the MAX5590/MAX5591, the 16 bits consist of 4 control bits (C3–C0) and 12 data bits (D11–D0) (see Table 1). For the 10-bit MAX5592/ MAX5593 devices, D11–D2 are the data bits and D1 and D0 are sub-bits. For the 8-bit MAX5594/ MAX5595 devices, D11–D4 are the data bits and D3–D0 are sub-bits. Set all sub-bits to zero for optimum performance. Each DAC channel includes two registers: an input register and the DAC register. At power-up, the DAC output is set according to the state of PU. The DACs are double-buffered, which allows any of the following for each channel: • Loading the input register without updating the DAC register • Updating the DAC register from the input register • Updating the input and DAC registers simultaneously

______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MSB

16 BITS OF SERIAL DATA

CONTROL BITS C3

C2

C1

LSB

DATA BITS C0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

tCH SCLK tCL tDS DIN

C3 tCS0

C2

C1

D0 tCSH

tDH tCSS

CS tCSW

tCS1 tDO1

DOUTDC1*

DOUT VALID tDO2

DOUTDC0 OR DOUTRB*

DOUT VALID

*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT). SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.

Figure 1. Serial-Interface Timing Diagram (DSP Mode Disabled) tCL SCLK tCH

tDS DIN

C3

C2

C1

D0

tCS0 tDH

tCSH

tCCS CS

tCSW

tCS1

tDSS tDS0

DSP tDSW

tD02

tDSPWL

DOUTDC0*

DOUT VALID tD01

DOUTDC1 OR DOUTRB*

DOUT VALID

*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT). SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.

Figure 2. Serial-Interface Timing Diagram (DSP Mode Enabled) ______________________________________________________________________________________

17

MAX5590–MAX5595

Table 1. Serial Write Data Format

MAX5590–MAX5595

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Serial-Interface Programming Commands

Loading Input and DAC Registers

Tables 2a, 2b, and 2c provide all of the serial-interface programming commands for the MAX5590–MAX5595. Table 2a shows the basic DAC programming commands, Table 2b gives the advanced-feature programming commands, and Table 2c provides the 24-bit read commands. Figures 3 and 4 provide the serialinterface diagrams for read and write operations.

The MAX5590–MAX5595 contain a 16-bit shift register that is followed by a 12-bit input register and a 12-bit DAC register for each channel (see the Functional Diagrams). Tables 3, 4, and 5 highlight a few of the commands that handle the loading of the input and DAC registers. See Table 2a for all DAC programming commands.

VDD

MICROWIRE

VDD

SPI OR QSPI

VDD

DVDD

SK SO

DSP SCLK DIN

I/O

CS

MAX5590– MAX5595

VDD

DVDD

SCK MOSI

DSP SCLK DIN

COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N ✕ 16

CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION

CS

CS

SS OR I/O

MICROWIRE OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:

MAX5590– MAX5595

SCLK

DIN

C3

C2

C1

C0

D11

D10

D9

D8

D7

D6

D5

D4

SPI (CPOL = 1, CPHA = 1) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:

D2

D1

D0

COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N ✕ 16

CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION

CS

D3

SCLK

DIN

C3

C2

C1

C0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 3. MICROWIRE and SPI Single DAC Writes (CPOL = 0, CPHA = 0 or CPOL = 1, CPHA = 1)

DSP

SPI OR QSPI

MAX5590– DGND MAX5595

VSS

MAX5590–

DSP SCLK DIN

TCLK, SCLK, OR CLKX DT OR DX

CS

SS OR I/O

DSP OR SPI (CPOL = 0, CPHA = 1) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:

COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N ✕ 16

CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION

CS

DSP SCLK DIN

SCK MOSI

CS

TFS OR FSX

DGND MAX5595

VSS

SCLK

DIN

C3

C2

C1

C0

D11

D10

D9

D8

D7

D6

D5

D4

DSP OR SPI (CPOL = 1, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:

D2

D1

D0

COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N ✕ 16

CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION

CS

D3

SCLK

DIN

C3

C2

C1

C0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 4. DSP and SPI Single DAC Writes (CPOL = 0, CPHA = 1 or CPOL = 1, CPHA = 0) 18

______________________________________________________________________________________

C3

C2

C1

______________________________________________________________________________________

0

0

0

0

0

0

0

DIN

DIN

DIN

DIN

DIN

DIN

DIN

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

D11 D10

D11 D10

D11 D10

D11 D10

D11 D10

D11 D10

D11 D10

D11 D10

D11 D10

D9

D9

D9

D9

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D5

D5

D5

D5

DATA BITS D3

D2

D1

D0

FUNCTION

Load input register H from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*

Load input register G from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*

Load input register F from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*

Load input register E from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*

Load input register D from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*

Load input register C from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*

Load input register B from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*

Load input register A from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*

D4

MAX5590–MAX5595

*For the MAX5592/MAX5593 (10-bit version), D11–D2 are the significant bits and D1 and D0 are sub-bits. For the MAX5594/MAX5595 (8-bit version), D11–D4 are the significant bits and D3–D0 are sub-bits. Set all sub-bits to zero during the write commands.

0

DIN

0

C0

CONTROL BITS

INPUT REGISTERS (A–H)

DATA

Table 2a. DAC Programming Commands

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs

19

20

C3

1

0

C2

0

C1

CONTROL BITS

0

C0

X

D11

1

DIN

0

0

1

DIN

0

______________________________________________________________________________________

0

1

X

DIN

DOUTRB

X

X

1

1

X

1

1

X

1

1

1

0

X

1

1

X

1

1

X

1

1

0

1

X

0

0

X

0

0

X

0

0

D11

D11

X

1

1

X

0

0

X

0

0

D10

D10

X

0

0

X

1

1

X

0

0

D9

D9

X

D9

X

1

0

X

1

0

X

1

0

D8

D8

X

D8

D6

D6

MG

D6

D5

D5

MF

D5

DATA BITS

D4

D4

ME

D4

D3/0

D3/0

MD

D3

D2/0

D2/0

MC

D2

D1/0

D1/0

MB

D1

Load DAC register “_” from input register “_” when M_ = 1. DAC register “_” is unchanged if M_ = 0.

FUNCTION

Load all input and DAC registers A–H from shift D0/0 register. DAC outputs updated.

Load all input registers A–H from shift register; D0/0 DAC registers are unchanged. DAC outputs are unchanged.*

MA

D0

Write DAC shutdowncontrol bits. X X X X X X X X Read-back DAC PDCH PDCG PDCF PDCE PDCD PDCC PDCB PDCA shutdown-control settings.

PDCH PDCG PDCF PDCE PDCD PDCC PDCB PDCA

X X X X X X X X Read-back DACE–DACH PDH1 PDH0 PDG1 PDG0 PDF1 PDF0 PDE1 PDE0 shutdown-mode bits.

Write DACE–DACH PDH1 PDH0 PDG1 PDG0 PDF1 PDF0 PDE1 PDE0 shutdown-mode bits. See Table 8.

X X X X X X X X Read-back DACA–DACD PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0 shutdown-mode bits.

Write DACA–DACD PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0 shutdown-mode bits. See Table 8.

D7

D7

MH

D7

*For the MAX5592/MAX5593 (10-bit version), D11–D2 are the significant bits and D1 and D0 are sub-bits. For the MAX5594/MAX5595 (8-bit version), D11–D4 are the significant bits and D3–D0 are sub-bits. Set all sub-bits to zero during the write commands.

X = Don’t care.

0

1

DIN

X

1

X

DIN

DOUTRB

X

1

X

DIN

0

1

0

0

DOUTRB

DIN

SHUTDOWN BITS

1

DIN

X

D10

LOADING INPUT AND DAC REGISTERS (A–H)

DIN

SELECT BITS

DATA

Table 2b. Advanced-Feature Programming Commands

MAX5590–MAX5595 Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs

C2

C1

CONTROL BITS

0

1

X

DIN

DOUTRB

X

1

1

0

1

X

DIN

DOUTRB

X

1

1

X

1

1

X

1

1

C0

X

1

1

X

0

0

D11

X

DOUTRB

X

0

X

1

X

1

1

X

DIN

DOUTRB

X = Don’t care.

1

DIN

X

1

1

X

0

0

X

0

0

CPOL AND CPHA CONTROL BITS

1

DIN

X

0

0

X

1

UPIO_ AS GPI (GENERAL-PURPOSE INPUT)

X

0

1

DIN

SETTLING-TIME-MODE BITS

X

0

1

DIN

UPIO CONFIGURATION BITS

C3

X

0

0

X

0

X

0

0

X

1

1

D10

X

0

0

X

1

X

0

0

X

1

1

D9

X

1

0

X

X

X

1

0

X

1

0

D8

D6

D5

DATA BITS

UP2

D4

UP1

D3

UP0

D2

X

D1

X

D0 Write UPIO configuration bits. See Tables 19 and 22.

FUNCTION

X

X

X

X

X

X

X

X

X

X

X

X

X

RTP2

X

X

X

X

LF2

X

X

X

X

LR2

X

X

X

X

RTP1

X

LR1

X

X

Write CPOL, CPHA control bits. See Table 15.

Read UPIO_ inputs (valid only when UPIO1 or UPIO2 is configured as a generalpurpose input.) See the GPI, GPOL, GPOH section.

Read CPOL, CPHA control CPOL CPHA bits.

X

CPOL CPHA

LF1

X

X X X X X X X X Read-back DAC settlingSPDH SPDG SPDF SPDE SPDD SPDC SPDB SPDA time bits.

Write settling-time bits for DACA–DACH (0 = SLOW SPDH SPDG SPDF SPDE SPDD SPDC SPDB SPDA [default, 6µs], 1 = FAST [3µs]).

X X X X X X X X Read-back UPIO UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1 configuration bits function.

UPSL2 UPSL1 UP3

D7

MAX5590–MAX5595

DATA

Table 2b. Advanced-Feature Programming Commands (continued)

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs

______________________________________________________________________________________

21

CONTROL BITS

X

1

X

1

X

1

X

1

X

1

X

1

X

1

X

DOUTRB

DIN

DOUTRB

DIN

DOUTRB

DIN

DOUTRB

DIN

DOUTRB

DIN

DOUTRB

DIN

DOUTRB

DIN

DOUTRB

X

1

X

1

X

1

X

1

X

1

X

1

X

1

X

1

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

1

X

1

X

1

X

1

X

1

X

1

X

1

X

1

X

1

X

1

X

1

X

1

X

0

X

0

X

0

X

0

X

1

X

1

X

0

X

0

X

1

X

1

X

0

X

0

X

1

X

0

X

1

X

0

X

1

X

0

X

1

X

0

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

1

D23

1

1

1

1

1

1

1

D22

1

1

1

1

1

1

1

D21

1

1

1

1

1

1

1

D20

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

D13 D12

DATA BITS D19 D18 D17 D16 D15 D14

1

1

1

1

1

1

1

D11

1

1

1

1

1

1

1

D10

1

1

1

1

1

1

1

D9

1

1

1

1

1

1

1

D8

1

1

1

1

1

1

X

D7

X

X

X

X

X

X

X

D6

X

X

X

X

X

X

X

D5

X

X

X

X

X

X

X

D4

X

X

X

X

X

X

X

D3

X

X

X

X

X

X

X

D2

X

X

X

X

X

X

X

D1

X

X

X

X

X

X

X

D0

X

X

X

X

X

X

X

X

X

X

X

X

X

X

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Read input register H and DAC register H (all 24 bits).**†

Read input register G and DAC register G (all 24 bits).**†

Read input register F and DAC register F (all 24 bits).**†

Read input register E and DAC register E (all 24 bits).**†

Read input register D and DAC register D (all 24 bits).**†

Read input register C and DAC register C (all 24 bits).**†

Read input register B and DAC register B (all 24 bits).**†

Read input register A and DAC register A (all 24 bits).**†

FUNCTION

______________________________________________________________________________________

†During readback, all ones (code FF) must be clocked into DIN for all 24 bits. No command can be issued before all 24 bits have been clocked out. CS must be kept low while all 24 bits are being clocked out.

**D23–D12 represent the 12-bit data from the corresponding DAC register. D11–D0 represent the 12-bit data from the corresponding input register. For the MAX5592/MAX5593, bits D13, D12, D1, and D0 are zero bits. For the MAX5594/MAX5595, bits D15–D12 and D3–D0 are zero bits.

X = Don’t care.

1

DIN

READ INPUT AND DAC REGISTERS A–H

C3 C2 C1 C0 D27 D26 D25 D24

DDH_11

DATA

Table 2c. 24-Bit Read Commands

DDA_11 DDB_11 DDC_11 DDD_11 DDE_11 DDF_11 DDH_10

DDG_11

DDA_10 DDB_10 DDC_10 DDD_10 DDE_10 DDF_10 DDH_9

DDG_10

DDA_9 DDB_9 DDC_9 DDD_9 DDE_9 DDF_9 DDH_8

DDG_9

DDA_8 DDB_8 DDC_8 DDD_8 DDE_8 DDF_8 DDH_7

DDG_8

DDA_7 DDB_7 DDC_7 DDD_7 DDE_7 DDF_7 DDH_6

DDG_7

DDA_6 DDB_6 DDC_6 DDD_6 DDE_6 DDF_6 DDH_5

DDG_6

DDA_5 DDB_5 DDC_5 DDD_5 DDE_5 DDF_5 DDH_4

DDG_5

DDA_4 DDB_4 DDC_4 DDD_4 DDE_4 DDF_4 DDH_3

DDG_4

DDA_3 DDB_3 DDC_3 DDD_3 DDE_3 DDF_3 DDH_2

DDG_3

DDA_2 DDB_2 DDC_2 DDD_2 DDE_2 DDF_2 DDH_1

DDG_2

DDA_1 DDB_1 DDC_1 DDD_1 DDE_1 DDF_1 DDH_0

DDG_1

DDA_0 DDB_0 DDC_0 DDD_0 DDE_0 DDF_0 IDH_11

DDG_0

IDA_11 IDB_11 IDC_11 IDD_11 IDE_11 IDF_11 IDH_10

IDG_11

IDA_10 IDB_10 IDC_10 IDD_10 IDE_10 IDF_10

IDA_9 IDB_9 IDC_9 IDD_9 IDE_9 IDF_9 IDH_9

IDG_9

IDA_8 IDB_8 IDC_8 IDD_8 IDE_8 IDF_8 IDH_8

IDG_8

IDA_7 IDB_7 IDC_7 IDD_7 IDE_7 IDF_7 IDH_7

IDG_7

IDA_6 IDB_6 IDC_6 IDD_6 IDE_6 IDF_6 IDH_6

IDG_6

IDA_5 IDB_5 IDC_5 IDD_5 IDE_5 IDF_5 IDH_5

IDG_5

IDA_4 IDB_4 IDC_4 IDD_4 IDE_4 IDF_4 IDH_4

IDG_4

IDA_3 IDB_3 IDC_3 IDD_3 IDE_3 IDF_3 IDH_3

IDG_3

IDA_2 IDB_2

IDA_1 IDB_1 IDC_1 IDD_1

IDC_2 IDD_2 IDE_2 IDF_2

IDE_1 IDF_1 IDH_2

IDG_2

IDH_1

IDG_1

IDA_0 IDB_0 IDC_0 IDD_0 IDE_0 IDF_0 IDG_0 IDH_0

22 IDG_10

MAX5590–MAX5595 Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Select Bits (M_) The select bits allow synchronous updating of any combination of channels. The select bits command the loading of the DAC register from the input register of each channel. Set the select bit M_ = 1 to load the DAC register “_” with data from the input register “_”, where “_” is replaced with A, B, or C and so on through H, depending on the selected channel. Setting the select bit M_ = 0 results in no action for that channel (Table 6). Select Bits Programming Example: To load DAC register B from input register B while keeping other channels (A, C–H) unchanged, set MB = 1 and M_ = 0 (Table 7).

Table 3. Load Input Register A from Shift Register DATA DIN

CONTROL BITS 0

0

0

DATA BITS 0

D11

D10

D9

D8

D7

D6

D5

D4

D3/0

D2/0

D1/0

D0/0

D4

D3/0

D2/0

D1/0

D0/0

Table 4. Load Input Registers (A–H) from Shift Register DATA DIN

CONTROL BITS 1

0

0

DATA BITS 1

D11

D10

D9

D8

D7

D6

D5

Table 5. Load Input Registers (A–H) and DAC Registers (A–H) from Shift Register DATA DIN

CONTROL BITS 1

0

1

DATA BITS 0

D11

D10

D9

D8

D7

D6

D5

D4

D3/0

D2/0

D1/0

D0/0

MC

MB

MA

0

1

0

Table 6. Select Bits (M_) DATA DIN

CONTROL BITS 1

0

0

0

X

DATA BITS X

X

X

MH

MG

MF

ME

MD

X = Don’t care.

Table 7. Select Bits Programming Example DATA DIN

CONTROL BITS 1

0

0

0

X

DATA BITS X

0

0

0

0

0

0

0

X = Don’t care.

______________________________________________________________________________________

23

MAX5590–MAX5595

Advanced-Feature Programming Commands

DAC Programming Examples: To load input register A from the shift register, leaving DAC register A unchanged (DAC output unchanged), use the command in Table 3. The MAX5590–MAX5595 can load all of the input registers (A–H) simultaneously from the shift register, leaving the DAC registers unchanged (DAC output unchanged), by using the command in Table 4. To load all of the input registers (A–H) and all of the DAC registers (A–H) simultaneously, use the command in Table 5. For the 10-bit and 8-bit versions, set sub-bits = 0 for best performance.

MAX5590–MAX5595

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Shutdown-Mode Bits (PD_0, PD_1) Use the shutdown-mode bits and control bits to shut down each DAC independently. The shutdownmode bits determine the output state of the selected channels. The shutdown-control bits put the selected channels into shutdown-mode. To select the shutdown mode for DACA–DACH, set PD_0 and PD_1 according to Table 8 (where “_” is replaced with one of the selected channels (A–H)). The three possible states for unitygain versions are 1) normal operation, 2) shutdown with

1kΩ output impedance, and 3) shutdown with 100kΩ output impedance. The three possible states for forcesense versions are 1) normal operation, 2) shutdown with 1kΩ output impedance, and 3) shutdown with the output in a high-impedance state. Tables 9 and 10 show the commands for writing to the shutdown-mode bits. Table 11 shows the commands for writing the shutdown-control bits. This command is required to put the selected channels into shutdown. Always write the shutdown-mode-bits command first and then write the shutdown-control-bits command to properly shut down the selected channels. The shutdown-control-bits command can be written at any time after the shutdown-mode-bits command. It does not have to immediately follow the shutdown-mode-bits command.

Table 8. Shutdown-Mode Bits PD_1

PD_0

DESCRIPTIONS

0

Shutdown with 1kΩ termination to ground on DAC_ output.

0

1

Shutdown with 100kΩ termination to ground on DAC_ output for unity-gain versions. Shutdown with high-impedance output for force-sense versions.

1

0

Ignored.

1

1

DAC_ is powered up in its normal operating mode.

0

Settling-Time-Mode Bits (SPD_) The settling-time-mode bits select the settling time (FAST mode or SLOW mode) of the MAX5590–MAX5595. Set SPD_ = 1 to select FAST mode or set SPD_ = 0 to select SLOW mode, where “_” is replaced by A, B, or C and so on through H, depending on the selected channel (Table 12). FAST mode provides a 3µs maximum settling time, and SLOW mode provides a 6µs maximum settling time.

Table 9. Shutdown-Mode Write Command (DACA–DACD) DATA DIN

CONTROL BITS 1

0

1

DATA BITS 1

0

0

0

0

PDD1 PDD0 PDC1 PDC0

PDB1

PDB0

PDA1

PDA0

PDF1

PDF0

PDE1

PDE0

X = Don’t care.

Table 10. Shutdown-Mode Write Command (DACE–DACH) DATA DIN

CONTROL BITS 1

0

1

DATA BITS 1

0

0

1

0

PDH1 PDH0 PDG1 PDG0

X = Don’t care.

Table 11. Shutdown-Control-Bits Write Command DATA DIN

CONTROL BITS 1

0

1

DATA BITS 1

0

1

0

0

PDCH PDCG PDCF PDCE PDCD PDCC PDCB PDCA

X = Don’t care.

Table 12. Settling-Time-Mode Write Command DATA DIN

24

CONTROL BITS 1

0

1

1

1

DATA BITS 0

0

0

SPDH SPDG SPDF

SPDE

SPDD SPDC SPDB SPDA

______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs

CPOL and CPHA Control Bits The CPOL and CPHA control bits of the MAX5590–MAX5595 are defined the same as the CPOL and CPHA bits in the SPI standard. Set the DAC’s CPOL and CPHA bits to CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1 for MICROWIRE and SPI applications requiring the clocking of data in on the ris-

To read back the device’s CPOL and CPHA bits, use the command in Table 17.

Table 13. Settling-Time-Mode Write Example DATA DIN

CONTROL BITS 1

0

DATA BITS

1

1

1

0

0

0

X

X

X

X

1

0

0

1

X

X

X

X = Don’t care.

Table 14. Settling-Time-Mode Read Command DATA

CONTROL BITS

DATA BITS

DIN

1

0

1

1

1

0

0

1

DOUTRB

X

X

X

X

X

X

X

X

X

X

X

X

X

SPDH SPDG SPDF SPDE SPDD SPDC SPDB SPDA

X = Don’t care.

Table 15. CPOL and CPHA Bits CPOL

CPHA

DESCRIPTION

0

0

Default values at power-up when DSP is connected to DVDD. Data is clocked in on the rising edge of SCLK.

0

1

Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge of SCLK.

1

0

Data is clocked in on the falling edge of SCLK.

1

1

Data is clocked in on the rising edge of SCLK.

Table 16. CPOL and CPHA Write Command DATA DIN

CONTROL BITS 1

1

0

DATA BITS 0

0

0

0

0

X

X

X

X

X

X

CPOL CPHA

X = Don’t care.

Table 17. CPOL and CPHA Read Command DATA

CONTROL BITS

DATA BITS

DIN

1

1

0

0

0

0

0

1

X

X

X

X

X

X

DOUTRB

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

CPOL CPHA

X = Don’t care. ______________________________________________________________________________________

25

MAX5590–MAX5595

ing edge of SCLK. Set the DAC’s CPOL and CPHA bits to CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA = 0 for DSP and SPI applications, requiring the clocking of data in on the falling edge of SCLK (refer to the Programmer’s Handbook and see Table 15 for details). At power-up, if DSP = DVDD, the default value of CPHA is zero and if DSP = DGND, the default value of CPHA is one. The default value of CPOL is zero at power-up. To write to the CPOL and CPHA bits, use the command in Table 16.

Settling-Time-Mode Write Example: To configure DACA and DACD into FAST mode and DACB and DACC into SLOW mode, use the command in Table 13. To read back the settling-time-mode bits, use the command in Table 14.

MAX5590–MAX5595

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs UPIO Bits (UPSL1, UPSL2, UP0–UP3) The MAX5590–MAX5595 provide two user-programmable input/output (UPIO) ports: UPIO1 and UPIO2. These ports have 15 possible configurations, as shown in Table 22. UPIO1 and UPIO2 can be programmed independently or simultaneously by writing to the UPSL1, UPSL2, and UP0–UP3 bits (Table 18). Table 19 shows how UPIO1 and UPIO2 are selected for configuration. The UP0–UP3 bits select the desired functions for UPIO1 and/or UPIO2 (Table 22).

UPIO Programming Example: To set only UPIO1 as LDAC and leave UPIO2 unchanged, use the command in Table 20. The UPIO selection and configuration bits can be read back from the MAX5590–MAX5595 when UPIO1 or UPIO2 is configured as a DOUTRB output. Table 21 shows the read-back data format for the UPIO bits. Writing the command in Table 21 initiates a read operation of the UPIO bits. The data is clocked out starting on the ninth clock cycle of the sequence. Bits UP3-2 through UP0-2 provide the UP3–UP0 configuration bits for UPIO2 (Table 22), and bits UP3-1 through UP0-1 provide the UP3–UP0 configuration bits for UPIO1.

Table 18. UPIO Write Command DATA DIN

CONTROL BITS 1

0

1

DATA BITS 1

0

1

1

0

UPSL2 UPSL1

UP3

UP2

UP1

UP0

X

X

X = Don’t care.

Table 19. UPIO Selection Bits (UPSL1 and UPSL2) UPSL2

UPSL1

UPIO PORT SELECTED

0

0

None selected

0

1

UPIO1 selected

1

0

UPIO2 selected

1

1

Both UPIO1 and UPIO2 selected

Table 20. UPIO Programming Example DATA DIN

CONTROL BITS 1

0

1

DATA BITS 1

0

1

1

0

0

1

0

0

0

0

X

X

X

X

X

X

X

X = Don’t care.

Table 21. UPIO Read Command DATA

CONTROL BITS

DATA BITS

DIN

1

0

1

1

0

1

1

1

DOUTRB

X

X

X

X

X

X

X

X

X

X

X

UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1

X = Don’t care.

26

______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs

LDAC LDAC controls the loading of the DAC registers. When LDAC is high, the DAC registers are latched, and any change in the input registers does not affect the contents of the DAC registers or the DAC outputs. When LDAC is low, the DAC registers are transparent, and the values stored in the input registers are fed directly to the DAC registers, and the DAC outputs are updated.

Drive LDAC low to asynchronously load the DAC registers from their corresponding input registers (DACs that are in shutdown remain shut down). The LDAC input does not require any activity on CS, SCLK, or DIN to take effect. If LDAC is brought low coincident with a rising edge of CS (which executes a serial command modifying the value of either DAC input register), then LDAC must remain asserted for at least 120ns following the CS rising edge. This requirement applies only for serial commands that modify the value of the DAC input registers. See Figures 5 and 6 for timing details.

Table 22. UPIO Configuration Register Bits (UP3–UP0) UPIO CONFIGURATION BITS

FUNCTION

DESCRIPTION

UP3

UP2

UP1

UP0

0

0

0

0

LDAC

0

0

0

1

SET

Active-Low Input. Drive low to set all input and DAC registers to full scale.

0

0

1

0

MID

Active-Low Input. Drive low to set all input and DAC registers to midscale.

0

0

1

1

CLR

Active-Low Input. Drive low to set all input and DAC registers to zero scale.

0

1

0

0

PDL

Active-Low Power-Down Lockout Input. Drive low to disable software shutdown.

0

1

0

1

Reserved

This mode is reserved. Do not use.

SHDN1K

Active-Low 1kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the MAX5590/MAX5592/MAX5594, drive SHDN1K low to pull OUTA–OUTH to AGND with 1kΩ. For the MAX5591/MAX5593/MAX5595, drive SHDN1K low to leave OUTA–OUTH high impedance.

0

1

1

0

Active-Low Load DAC Input. Drive low to asynchronously load all DAC registers with data from input registers.

Active-Low 100kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the MAX5590/MAX5592/MAX5594, drive SHDN100K low to pull OUTA–OUTH to AGND with 100kΩ. For the MAX5591/MAX5593/MAX5595, drive low to leave OUTA–OUTH high impedance.

0

1

1

1

SHDN100K

1

0

0

0

DOUTRB

1

0

0

1

DOUTDC0

1

0

1

0

DOUTDC1

1

0

1

1

GPI

1

1

0

0

GPOL

General-Purpose Logic-Low Output

1

1

0

1

GPOH

General-Purpose Logic-High Output

1

1

1

0

TOGG

Toggle Input. Toggles DAC outputs between data in input registers and data in DAC registers. Drive low to set all DAC outputs to values stored in input registers. Drive high to set all DAC outputs to values stored in DAC registers.

1

1

1

1

FAST

Fast/Slow Settling-Time-Mode Input. Drive low to select FAST (3µs) mode or drive high to select SLOW (6µs) settling mode. Overrides the SPDA–SPDH settings.

Data Read-Back Output Mode 0 Daisy-Chain Data Output. Data is clocked out on the falling edge of Mode 1 Daisy-Chain Data Output. Data is clocked out on the rising edge of SCLK. General-Purpose Logic Input

______________________________________________________________________________________

27

MAX5590–MAX5595

UPIO Configuration Table 22 lists the possible configurations for UPIO1 and UPIO2. UPIO1 and UPIO2 use the selected function when configured by the UP3–UP0 configuration bits.

MAX5590–MAX5595

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs tLDL LDAC

END OF CYCLE*

TOGG

tGP

PDL GPO_ tCMS CLR, MID, OR SET

LDAC tS

tLDS

±0.5 LSB

VOUT_ PDL AFFECTS DAC OUPTUTS (VOUT_) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN.

* END-OF-CYCLE REPRESENTS THE RISING EDGE OF CS OR THE 16TH ACTIVE CLOCK EDGE, DEPENDING ON THE MODE OF OPERATION.

Figure 5. Asynchronous Signal Timing

Figure 6. GPO_ and LDAC Signal Timing

SET, MID, CLR The SET, MID, and CLR signals force the DAC outputs to full scale, midscale, or zero scale (Figure 5). These signals cannot be active at the same time. The active-low SET input forces the DAC outputs to full scale when SET is low. When SET is high, the DAC outputs follow the data in the DAC registers. The active-low MID input forces the DAC outputs to midscale when MID is low. When MID is high, the DAC outputs follow the data in the DAC registers. The active-low CLR input forces the DAC outputs to zero scale when CLR is low. When CLR is high, the DAC outputs follow the data in the DAC registers. If CLR, MID, or SET signals go low during a write command, reload the data to ensure accurate results.

SHDN1K low to select shutdown mode with OUTA– OUTH internally terminated with 1kΩ to ground, or drive SHDN100K low to select shutdown with an internal 100kΩ termination. For the MAX5591/MAX5593/ MAX5595, drive SHDN1K low for shutdown with 1kΩ output termination, or drive SHDN100K low for shutdown with high-impedance outputs. For proper shutdown, first select a shutdown mode (Table 8), then use the shutdown-control bits as listed in Table 2b.

Power-Down Lockout (PDL) The PDL active-low, software-shutdown lockout input overrides (not overwrites) the PD_0 and PD_1 shutdownmode bits. PDL cannot be active at the same time as SHDN1K or SHDN100K (see the Shutdown Mode (SHDN1K, SHDN100K) section). If the PD_0 and PD_1 bits command the DAC to shut down prior to PDL going low, the DAC returns to shutdown mode immediately after PDL goes high, unless the PD_0 and PD_1 bits were modified through the serial interface in the meantime.

SHDN1K, SHDN100K) Shutdown Mode (S The SHDN1K and SHDN100K are active-low signals that override (not overwrite) the PD_1 and PD_0 bit settings. For the MAX5590/MAX5592/MAX5594, drive

28

Data Output (DOUTRB, DOUTDC0, DOUTDC1) UPIO1 and UPIO2 can be configured as serial data outputs, DOUTRB (data out for read back), DOUTDC0 (data out for daisy-chaining, mode 0), and DOUTDC1 (data out for daisy-chaining, mode 1). The differences between DOUTRB and DOUTDC0 (or DOUTDC1) are as follows: • The source of read-back data on DOUTRB is the DOUT register. Daisy-chain DOUTDC_ data comes directly from the shift register. • Read-back data on DOUTRB is only present after a DAC read command. Daisy-chain data is present on DOUTDC_ for any DAC write after the first 16 bits are written. • The DOUTRB idle state (CS = high) for read back is high impedance. Daisy-chain DOUTDC_ idles high when inactive to avoid floating the data input in the next device in the daisy-chain. See Figures 1 and 2 for timing details.

______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs GPOL outputs a constant low, and GPOH outputs a constant high. See Figure 6.

TOGG Use the TOGG input to toggle the DAC outputs between the values in the input registers and DAC registers. A delay of greater than 100ns from the end of the previous write command is required before the TOGG signal can be correctly switched between the new value and the previously stored value. When TOGG = 0, the output follows the information in the input registers. When TOGG = 1, the output follows the information in the DAC register (Figure 5).

1) Sample the signal at GPI at the time of the read (RTP1 and RTP2). 2) Detect whether or not a falling edge has occurred since the last read or reset (LF1 and LF2). 3) Detect whether or not a rising edge has occurred since the last read or reset (LR1 and LR2). RTP1, LF1, and LR1 represent the data read from UPIO1; RTP2, LF2, and LR2 represent the data read from UPIO2. To issue a read command for the UPIO configured as GPI, use the command in Table 23. Once the command is issued, RTP1 and RTP2 provide the real-time status (0 or 1) of the inputs at UPIO1 or UPIO2, respectively, at the time of the read. If LF2 or LF1 is one, then a falling edge has occurred on the respective UPIO1 or UPIO2 input since the last read or reset. If LR2 or LR1 is one, then a rising edge has occurred since the last read or reset.

FAST The MAX5590–MAX5595 have two settling-time-mode options: FAST (3µs max) and SLOW (6µs max). To select the FAST mode, drive FAST low, and to select SLOW mode, drive FAST high. This overrides (not overwrites) the SPDA–SPDH bit settings.

Table 23. GPI Read Command DATA

CONTROL BITS

DATA BITS

DIN

1

0

1

1

1

0

1

X

X

X

X

X

X

X

X

X

DOUTRB

X

X

X

X

X

X

X

X

X

X

RTP2

LF2

LR2

RTP1

LF1

LR1

X = Don’t care.

Table 24. Unipolar Code Table (Gain = +1) DAC CONTENTS MSB

LSB

ANALOG OUTPUT

REF_

DAC_ OUT_

1111

1111

1111

+VREF (4095 / 4096)

1000

0000

0001

+VREF (2049 / 4096)

1000

0000

0000

+VREF (2048 / 4096) = VREF / 2

0111

1111

1111

+VREF (2047 / 4096)

0000

0000

0001

+VREF (1 / 4096)

0000

0000

0000

0

VOUT_ = VREF_ x CODE / 4096 CODE IS THE DAC_ INPUT CODE (0 TO 4095 DECIMAL).

MAX5590

Figure 7. Unipolar Output Circuit

______________________________________________________________________________________

29

MAX5590–MAX5595

GPI, GPOL, GPOH UPIO1 and UPIO2 can each be configured as a general-purpose input (GPI), a general-purpose output low (GPOL), or a general-purpose output high (GPOH). The GPI can serve to detect interrupts from µPs or microcontrollers. The GPI has three functions:

MAX5590–MAX5595

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Applications Information Unipolar Output Figure 7 shows the unity-gain MAX5590 in a unipolar output configuration. Table 24 lists the unipolar output codes.

10kΩ

10kΩ V+

Bipolar Output The MAX5590 outputs can be configured for bipolar operation, as shown in Figure 8. The output voltage is given by the following equation: VOUT_ = VREF x (CODE - 2048) / 2048 where CODE represents the numeric value of the DAC’s binary input code (0 to 4095 decimal). Table 25 shows digital codes and the corresponding output voltage for the Figure 8 circuit.

VOUT DAC_ REF

OUT_ V-

MAX5590

Configurable Output Gain The MAX5591/MAX5593/MAX5595 have force-sense outputs, which provide a direct connection to the inverting terminal of the output op amp, yielding the most flexibility. The force-sense output has the advantage that specific gains can be set externally for a given application. The gain error for the MAX5591/MAX5593/ MAX5595 is specified in a unity-gain configuration (opamp output and inverting terminals connected), and additional gain error results from external resistor tolerances. The force-sense DACs allow many useful circuits to be created with only a few simple external components. An example of a custom, fixed gain using the MAX5591’s force-sense output is shown in Figure 9. In this example, the external reference is set to 1.25V, and the gain is set to +1.1V/V with external discrete resistors to provide an approximate 0 to 1.375V DAC output voltage range. VOUT = [(0.5 x VREF_ x CODE) / 4096] x [1 + (R2 / R1)] where CODE represents the numeric value of the DAC’s binary input code (0 to 4095 decimal). In this example, R2 = 12kΩ and R1 = 10kΩ to set the gain = 1.1V/V. VOUT = [(0.5 x 1.25V x CODE) / 4096] x 2.2

Figure 8. Bipolar Output Circuit

REF

DAC_ OUT_ R2 = 12kΩ 0.1% 25ppm

R1 = 10kΩ 0.1% 25ppm

Figure 9. Configurable Output Gain

Table 25. Bipolar Code Table (Gain = +1) DAC CONTENTS MSB

30

FB_

MAX5591

LSB

ANALOG OUTPUT

1111

1111

1111

+VREF (2047 / 2048)

1000

0000

0001

+VREF (1 / 2048)

1000

0000

0000

0

0111

1111

1111

-VREF (1 / 2048)

0000

0000

0001

-VREF (2047 / 2048)

0000

0000

0000

-VREF (2048 / 2048) = -VREF

______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs

AVDD

AVDD

Using separate power supplies for AVDD and DVDD improves noise immunity. Connect AGND and DGND at the low-impedance power-supply sources (Figure 11).

DVDD

0.1µF VREF

inductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use PC boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance power-supply source.

10µF

0.1µF

10µF

DVDD

ANALOG SUPPLY

DIGITAL SUPPLY

AVDD

DVDD

AGND

DGND

REF 10µF*

0.1µF*

OUTA

MAX5590–MAX5595

CS SCLK DIN

10µF

10µF

0.1µF

0.1µF

OUTH

PU MAX5591 MAX5593 MAX5595 ONLY

DSP UPIO1 UPIO2 AGND**

FBA

FBH

DGND**

AVDD

AGND

DVDD

MAX5590–MAX5595

DGND

DVDD

DGND

DIGITAL CIRCUITRY

*REMOVE BYPASS CAPACITORS ON REF FOR AC-REFERENCE INPUTS. **CONNECT ANALOG AND DIGITAL GROUND PLANES AT THE LOW-IMPEDANCE POWER-SUPPLY SOURCE.

Figure 10. Bypassing Power Supplies AVDD, DVDD, and REF

Figure 11. Separate Analog and Digital Power Supplies

______________________________________________________________________________________

31

MAX5590–MAX5595

Power-Supply and Layout Considerations Bypass the analog and digital power supplies by using a 10µF capacitor in parallel with a 0.1µF capacitor to AGND and DGND (Figure 10). Minimize lead lengths to reduce lead inductance. Use shielding and/or ferrite beads to further increase isolation. Digital and AC transient signals coupling to AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low-

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590–MAX5595

Pin Configurations TOP VIEW

+ AVDD 1

+

24 REF

AGND 2

23 PU

OUTA 3

22 OUTH

N.C. 4

21 N.C.

OUTB 5 OUTC 6

MAX5590 MAX5592 MAX5594

N.C. 8

17 N.C.

CS 9

16 UPIO2

SCLK 10

15 UPIO1

DIN 11

14 DGND

DSP 12

13 DVDD

AGND 2

27 PU

OUTA 3

26 OUTH 25 FBH

FBB 5 OUTB 6

19 OUTF 18 OUTE

28 REF

FBA 4

20 OUTG

OUTD 7

AVDD 1

OUTC 7

TSSOP

24 FBG

MAX5591 MAX5593 MAX5595

23 OUTG 22 OUTF

FBC 8

21 FBF

FBD 9

20 FBE

OUTD 10

19 OUTE

CS 11

18 UPIO2

SCLK 12

17 UPIO1

DIN 13

16 DGND

DSP 14

15 DVDD

TSSOP

Selector Guide PART

OUTPUT RESOLUTION BUFFER (BITS) CONFIGURATION

INL (LSBs MAX)

MAX5590AEUG+

Unity Gain

12

±1

MAX5590BEUG+

Unity Gain

12

±4

Chip Information PROCESS: BiCMOS

Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

MAX5591AEUI+

Force Sense

12

±1

MAX5591BEUI+

Force Sense

12

±4

MAX5592EUG+

Unity Gain

10

±1

MAX5593EUI+

Force Sense

10

±1

MAX5594EUG+

Unity Gain

8

±0.5

PACKAGE TYPE

PACKAGE CODE

DOCUMENT NO.

MAX5595EUI+

Force Sense

8

±0.5

24 TSSOP

U24+1

21-0066

28 TSSOP

U28+2

21-0066

32

______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs REVISION NUMBER

REVISION DATE

2

7/07

3

1/10

DESCRIPTION Updated EC table specifications

PAGES CHANGED 1, 6–9, 33

Added lead-free information and amended data sheet

1–13, 16, 20, 32, 33

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33 © 2010 Maxim Integrated Products

Maxim is a registered trademark of Maxim Integrated Products, Inc.

MAX5590–MAX5595

Revision History