ECE 485/585 Microprocessor System Design Lecture 6:

DDR, DDR2 and DDR-3 SDRAM Memory Modules

Zeshan Chishti Electrical and Computer Engineering Dept. Maseeh College of Engineering and Computer Science Source: Lecture based on materials provided by Mark F.

DDR (Double Data Rate) SDRAM  Innovation – Transfer data on rising and falling edges of clock  Same internal SDRAM core but 2n-prefetch

 Benefit – 2x the bandwidth, same control & signals as SDRAM  Significant Differences:  Source synchronous (DQS)  Burst length of 2,4,8 only  CL = 2, 2.5, 3

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DDR (Double Data Rate) SDRAM 

2n prefetch   



Use same DRAM core (cell array) Fetch twice as many bits Same latency for first data transfer

Source synchronous  

Data transfer is twice clock rate Data strobe sent alongside data 

Read: supplied by DRAM 



Write: supplied by controller 

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Data aligned with strobe edge Data centered on strobe edge

[from Elpida]

(cont’d)

DDR SDRAM Access Examples Reads from same open page/bank

Micron DDR Datasheet

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[From: Samsung]

Banks Incorporated Into SDRAM

Memory address Row

Bank

Column

 Why row/bank/column, not bank/row/column? 

Consider spatial locality



Imagine accessing a series of sequential memory addresses



After exhausting a column, references to another bank



Consider if row/bank reversed 

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Bank would rarely be used, lose benefit of interleaving

DDR SDRAM Access Examples Reads from different banks, open row

Row

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Memory address Bank

[From: Samsung]

Column

DDR SDRAM Access Examples Reads from different row

Memory address Bank ECE 485/585

Row

Column

From: Samsung

DDR-2 SDRAM 

During 2009-2010 the dominant high volume (PC) memory technology



Innovation – 4n-prefetch, faster clocks



Benefit – Increased bandwidth, same control/signals as DDR SDRAM



Significant Differences 

SSTL-18 (1.8V) vs. SSTL-2 (2.5V)



Low power (from lower supply voltage and new low power modes)



ODT (On Die Termination)



CL = 3,4,5



2Gb devices



4/8 banks vs. 4 banks 



Burst lengths of 4, 8 



tFAW = four-bank activation window

no 2 because of 4n-prefetch

“additive latency”

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Additive Latency

0

4

No additive latency, tRCD = CL = 4

Can’t place ACT command in cycle 4 slot occupied by RD AP: B0,Cx So ACT is delayed by full cycle so RD AP: B2, Cx is delayed and resulting data out is delayed

(from Micron

ACT B,R = activate row in bank RD AP B,C = read column from activated bank (auto pre-charge) ECE 485/585

Additive Latency

Can issue the RD B0,Cx command early (in available slot) No additive latency, t = CL = 4 but processing will still require adherence RCD to tRCD, CL timing constraints

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[from Micron]

Additive Latency

(cont’d)

No additive latency, tRCDavailable = CL = 4 Can issue the RD B0,Cx command early (in slot) but processing will still require adherence to tRCD, CL timing constraints

Permits continuous data read from DRAM

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(from Micron)

DDR-3  Key Differences (from DDR-2) 

8n prefetch



SSTL-15 (1.5V) vs. SSTL-18 (1.8V) 



667-800 MHz clocks 



Reduced power consumption (~30%) 2x bandwidth of DDR-2

8 banks vs. 4 banks 

More open banks – less latency

 Adoption rate 

Introduction in 2007 (insignificant quantities)



Samsung 8 Gb DDR3 described at ISSCC February 2009



Remained dominant PC memory until DDR-4 was introduced recently

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Micron DDR3 Datasheet

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DDR3 Commands

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DDR3 Read Cycle

Single read

Back-to-back reads to open page

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DRAM Speed and Size Trends 3500

65536

3200MHz

2500 2133MHz

2000 1500

1600MHz 1066MHz

1000

0

800MHz 400MHz 200MHz DDR

Device size (Mb)

Device speed (MHz)

3000

500

32Gb

16384 4096 1024

2Gb

1Gb

256 64

8Gb

4Gb

512Mb

256Mb 64Mb

16 4

400MHz

1 DDR2

DDR3

DDR4

DDR

DDR2

DDR3

 Higher memory bandwidth and capacity demand 

With help of process technology and VLSI advances



Resulted in to faster and bigger DRAM devices

 Latest DDR4 specifications 

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Up to 3.2Gbps and 32Gb devices

18

DDR4

DRAM Refresh  Leaky storage

 Periodic Refresh across DRAM rows  Un-accessible when refreshing  Read and write the same data back  Example: 

4K rows in a DRAM



100ns read cycle



Decay in 64ms

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Refresh Then: Asynchronous Interface

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DRAM Refresh Frequency  DRAM standard requires memory controllers to send periodic refresh commands to DRAM

tRefLatency (tRFC): Varies based on DRAM chip density (e.g., 350ns)

Timeline

tRefPeriod (tREFI): Remains constant (7.8 usec for Current generation DRAM)

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Refresh Now: N Simultaneous Rows CLK

CMD

PRE

REF

ACT

ADDR Bank/All

ROW

DATA tRP

Device densit y 8Gb

Num. Bank s 16

Perbank Rows 128K

Total Rows

Rows tRFC in AR (ɳs)

2M

256

350

16Gb

16

256K

4M

512

480

32Gb

16

512K

8M

1024 640

tRFC

 Command is called Auto-Refresh (AR)  Retention Time = 64ms  Refresh N rows in each 7.8 usec (64ms ÷ 8K), perbank  N increases with density (N: 16 8Gb, 32 16Gb)

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Impact of Refresh on Performance  DRAM is unavailable to serve requests for of time

tRefLatency tRefPeriod

 4.5% for today’s 4Gb DRAM  Unavailability increases with higher density due to higher tRefLatency

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Memory Modules

184 pin DDR SDRAM DIMM

 All chips in a “rank” receive same address and control signals  Each chip responsible for subset of data bits in its rank  Module acts as high capacity DRAM with wide data path 

Example: 8 chips, each 8 bits wide = 64 bits

 Easy to add/replace memory in a system 

No need to solder or remove individual chips

 Memory granularity issue 

What’s the smallest increment in memory size?

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From Hsien-Hsin Sean Lee, Georgia Institute of Technology

DRAM Ranks

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Organization of DRAM Modules

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Memory Modules 



 

SIMM (Single Inline Memory Module)  30-pin: some 286, most 386, some 486 systems – Page Mode, Fast Page mode devices  72-pin: some 386, most 486, nearly all Pentium (before DIMM) – Fast Page Mode, EDO devices DIMM (Dual Inline Memory Module)  Dominant today SODIMM (Small Outline DIMM)  Used in notebooks, Apple iMac RIMM (Rambus RDRAM Module)

SIMM

168 pin SDRAM DIMM

184 pin DDR SDRAM DIMM

200 pin DDR2, DDR3 SDRAM DIMM SODIMM

240 pin DDR2, DDR3 SDRAM DIMM

RIMM ECE 485/585

RIMM

SPD (Serial Presence Detect)  8-pin serial EEPROM on memory module  Key parameters for SDRAM controller       

Number of row/column addresses Number of ranks Module width Refresh rate/type Error checking (none, parity, ECC) Latency Timing parameters

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DRAM and DIMM Nomenclature Device name

Clock

M transfers per sec

MB/sec Per DIMM

DIMM name

DDR200

100 MHz

200

1,600 MB/s

PC-1600

DDR266

133 MHz

266

2,133 MB/s

PC-2100

DDR333

166 MHz

333

2,666 MB/s

PC-2700

DDR400

200 MHz

400

3,200 MB/s

PC-3200

DDR2-400

200 MHz

400

3,200 MB/s

PC2-3200

DDR2-533

266 MHz

533

4,266 MB/s

PC2-4200

DDR2-667

333 MHz

666

5,333 MB/s

PC2-5300

DDR2-800

400 MHz

800

6,400 MB/s

PC2-6400

DDR2-1066

533 MHz

1066

8,533 MB/s

PC2-8500

DDR3-800

400 MHz

800

6,400 MB/s

PC3-6400

DDR3-1066

533 MHz

1066

8,500 MB/s

PC3-8500

DDR3-1333

666 MHz

1333

10,666 MB/s

PC3-10600

DDR3-1600

800 MHz

1600

12,800 MB/s

PC3-12800

DDR3-1866

933 MHZ

1866

14928 MB/s

PC3-14900

M transfers/second = 2 transfers (DDR) x Clock Rate DRAM name incorporates M transfers per second MB/sec = 8 bytes x M transfers per second DIMM name incorporates MB/sec (rounded) ECE 485/585

DRAM/SDRAM Latency Specifications 





DRAM 

Used 4 numbers (e.g. 4-1-1-1)



Indicates number of CPU cycles for 1st and successive accesses

SDRAM 

CAS Latency (CAS or CL)



Delay in clock cycles between request and the time the first data is available



PC133 module might be described as CAS-2, CAS=2, CL2, CL-2, or CL=2

SDR-DRAM 



DDR-DRAM 





CAS Latency of 1, 2, or 3 CAS Latency of 2 or 2.5

When three numbers appear (e.g. 3-2-2) 

CAS Latency (tCAC)



RAS-to-CAS delay (tRCD)



RAS pre-charge time (tRP)

DDR3 seeing use of four numbers 

CAS Latency ( tCAS tCL, CL)



RAS-to-CAS delay (tRCD)



RAS pre-charge time (tRP)



RAS access time (tRAS)

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3-3-3-10 timing

Key SDRAM Timing Parameters 









tRCD:

Determines Latency



Minimum time between an ACTIVE command and READ command



Analogous to DRAM parameter tRCD : Row Command Delay (RAS/CAS Delay)

CL: CAS Latency

Determines Latency



Time between READ command and first data valid



Analogous to DRAM parameter tCAC: Column Access Time

tRAS 

Time between ACTIVE command and end of restoration of data in DRAM array



Analogous to DRAM parameter tRAS: Row Address Strobe

tRP 

Time to pre-charge DRAM array in preparation for another row access



Analogous to DRAM parameter tRP: Row Precharge Delay

tRC Determines Bandwidth 

Time between successive row access to different rows



tRC = tRAS + tRP



Analogous to DRAM parameter tRC: Row Cycle Time

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