Design & Verification Challenges for 3G/3.5G/4G Wireless Baseband MPSoCs
Michael Speth Herbert Dawid Frank Gersemsky Infineon Technologies AG Duisburg, Germany
Outline challenges of 3G / 4G modem design
data throughput
latency
configurability
wireless standards: a nightmare for system verification keys to success:
architecture
methodology
team-setup
03.07.2008
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State of the Art Cellphone Platform Focus: Digital Baseband
A Heterogeneous Application Specific Multi-Processor SoC 03.07.2008
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Example: Infineon MP-EH Platform
Customer Demands: 1. Functionality 2. Platform BOM 3. Power Consumption
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Why Dedicated Wireless MPSoCs? Thought Experiment: Modern digital cellular baseband ¬ 20 GOPs peak signal processing demand (active) ¬
0 GOPs computational demand (standby, paging)
¬ State of the art battery with 1400 mAh capacity
What if we use 2 general purpose processors (like the ones in your desktop PC), assuming they would be powerful enough? ¬ 60 W peak power consumption ¬ 20 W standby power consumption
Result
Active Time: 40 s
Standby Time: 30 min
We are building SoCs which are 100-1000x more energy efficient than state of the art GP processors and at the same time more efficient, faster, smaller and cheaper 03.07.2008
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Throughput
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Wireless Data Rate Evolution
NOMADIC/WLAN MAN / LAN / PAN
109
UWB 802.lln
! s h t on LTE
802.llag 802.llb Bluetooth
ng i l b Dou
Bits per second
106
M 6 1 ry E ve HSDPA UMTS
GSM
4G
3G
2G
Broadband Multimedia, Broadcast Video, High-Speed Packet Data
Multimedia Messaging, Medium-Speed, Packet Data
Digital Voice
CELLULAR
1 1992 03.07.2008
1996
2000
2004
2008
2012
Source: C. Drewes, Infineon Page 7
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How to Address the Challenge “Shannon beats Moore”
Increasing gap between chip technology and throughput requirements
Architecture + Algorithm
2G: DSP Centric Architectures
3.XG: + Dedicated HW Centric Architectures
4G
: + More Efficient Transmission Technology (OFDM) Throughput requirements are extremely tough but can be met with state of the art architectures + methodology
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Latency Requirements
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Network Modem Interaction Network View Radio Network Controller
Radio Network Controller
Base Stations
MRC
MRC
Closed Loop Transmit Diversity
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Highly advanced Signal Processing Algorithms plus Radio Link Adaptation and fast Scheduling Copyright © Infineon Technologies 2008. All rights reserved.
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Network Modem Interaction Digital Baseband Architectural View
3G Tx Framing & Channel Coding
3G Tx Modulator
3G RF Frontend
HSUPA HARQ DL Power Control HSUPA E-DCH E-TFC Selection HSDPA HARQ(ACK/NACK) (ACK/NACK) & CQI Intra-Frequency Measurements Modem Core SW Layer 1 Schedulers, FSMs, Drivers Physical Layer Re-Config Layer 2/3 Stack (MAC, RLC, RRC) Cell Search
AGC
Transport Channel Reconfig Soft Handover
Sync.
Layer 1 Schedulers, FSMs, Drivers
Delay Profile Estimation
TFCI 3G Inner Receiver
Data
L1 Config/Ctrl
3G Outer Receiver
System Information/Higher Layer Ctrl
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Example: 3G Power control Slot (2560 chips)
DL DPCCH at UTRAN
PILOT
T TF P CI C
Data1
Data2
Propagation delay DL-UL timing offset (1024 chips)
DL DPCCH at UE
PILOT
Data1
PILOT
T Data1 P C
Response To TPC (*3)
T TF P CI C
Data2
PILOT
Data1
T P C
512 chips DL SIR measurement (*1)
UL DPCCH at UE
PILOT
Response to TPC
TFCI
TPC
PILOT
Slot (2560 chips) Propagation delay
UL DPCCH at UTRAN *1,2
PILOT
UL SIR measurement (*2)
TFCI
TPC
PILOT
The SIR measurement periods illustrated here are examples. Other ways of measurement are allowed to achieve accurate SIR estimation. If there is not enough time for UTRAN to respond to the TPC, the action can be delayed until the next slot.
Latency + Reconfiguration dominates system architecture *3
Deterministic Scheduling is a must System Requirements must be known to the deepest detail 03.07.2008
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System Configurability
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Example: UMTS TX
TX accounts only for a few percent of silicon area + functionality
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TX Processing for UMTS Rel. 6 FW Config
extremely timing critical RX / TX interaction
Coding + Interleaving ~ 300 Parameters frame/subframe
source
coding
Modulation
Modulator: ~ 70 Parameters frame / slot Copyright © Infineon Technologies 2008. All rights reserved.
03.07.2008
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System Configurability 3G Transmitter:
Well defined serial bit processing
But: parameter flow can exceed data-flow
3G Receiver: much much more complicated
Multiple Base Stations, Soft Handover, Transmit Diversity
Multiple Rake Fingers, Receive Diversity
Complex Reconfigurations
Additional Neighbor Cell BCH
No exhaustive test possible Even minimum testing leads to thousands of complex test-cases 03.07.2008
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System Development and Bringup SW integration
HW issues SW issues Algorithm issues
Chip Developement
System Bringup
IOT
Live Network
Exhaustive verification impossible Flexibility required for very late changes 03.07.2008
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Architecture
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System Design Paradigms System Predictability Static real-time scheduling based on Worst Case Execution Times (WCETs) Limited HW-SW Interaction
Localized Functionality Divide Divide and and Conquer: Conquer: Cluster Cluster Functionality Functionality Æ Æ Æ Æ Æ Æ Æ Æ
HW-SW HW-SW Split: Split: Encapsulate Encapsulate Functionality Functionality in in HW HW Æ HW-SW Æ HW-SW Interface Interface Natural Natural Boundary Boundary for for Function Function Clusters Clusters Æ Latency Æ Latency Critical Critical Paths Paths in in HW HW Æ Simplified Æ Simplified SW SW Scheduling Scheduling Æ No Æ No Critical Critical HW-SW HW-SW Interactions Interactions
Self-Contained Self-Contained HW HW && FW FW Blocks Blocks Localized Localized Functionality, Functionality, Lean Lean Interfaces Interfaces Simplified Simplified Integration Integration && Verification Verification Sometimes Sometimes Extra Extra HW HW Needed Needed
Configuration Configuration Granularity: Granularity: UMTS UMTS Slot Slot (667 (667 µs) µs) and and Frame Frame (10 (10 ms) ms) Boundaries Boundaries Æ Æ
Performance vs Complexity
Simplified Simplified Verification Verification
Flexibility Where Needed Algorithm Algorithm Design: Design: Robust Robust and and “As “As Good Good As As Needed” Needed”
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03.07.2008
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Digital Baseband Detailed Architecture RAM/ ROM
µC (RTOS, Layer 1 SW + Protocol Stack)
Control Bus System IRQ IRQ IRQ
P
P
Chip Control HW Peripherals
Interface Bus Bus Interface Bus Interface
Reset Reset
Reset
Signal Processing Signal Processing Signal Processing HWHWHW Peripherals/DSPs Peripherals/DSPs Peripherals / DSPs / ASIPs Data Path Bus RAM
Separate functionality into autonomous subsystems 03.07.2008
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System Architecture Concept “System View“ Required (Cross-Layer, -Functional, -Disciplinary)
split up development in parallel streams
one team for each HW-Processing element
cross-functional setup
CE HW
FW CV
system level oriented flow for each sub-component: Compliance & IOT
Platform
Requirements Concept/Algorithm Design
System Integration
VP
HW/SW Architecture
Concurrent Development
HW/SW Integration
SW Design
Fine Architecture & VP Model RTL Design
Production Test Synthesis & Layout
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Team & Project Setup SW & FW Development
Architecture & Algorithm Design
Chip Development & Verification interdisciplinary interdisciplinaryteams: teams: Concept & Algorithms Concept & Algorithms HW HWdevelopment development SW development SW development System Systemverification verification 03.07.2008
joint responsibility
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Block Blocklevel leveldesign design&&verif. verif. Architecture refinement Architecture refinement HW/FW HW/FWcodesign codesign System integration System integration Page 22
Methodology
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Key Methodology: Virtual Prototype SW developers early SW integration on virtual hardware no pcb-limitation
VP
System architects explore/evaluate chip architectures by simulation
System testers early availability sophisticated debugging features no pcb-limitation
HW designers reference for verification (Executable Specification)
early proof of concept 03.07.2008
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Methodology: Bridging Levels of Abstraction 3GPP standard
test / regression system verification
verification
fast HW model
algo model
Test Config
VP
verification
verification code generation
code generation
SW
HW model interface description Copyright © Infineon Technologies 2008. All rights reserved.
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Methodology VP is the essential vehicle for system integration and verification Integrated tool landscape to provide maximum reuse Seamless transition between different levels of abstraction Platform for cross-functional team interaction Provide uniform touch-and-feel throughout all project phases
system architecture
methodology
team setup / processes 03.07.2008
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Conclusion Wireless SoC design is one of the biggest challenges in the industry Greatest challenge:
System reconfigurability
Latency critical loops
Not data-throughput
Success requires a system-level approach:
Exhaustive and detailed system knowledge
Interdisciplinary teams
Integrated design and verification flow
03.07.2008
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