2010 Agilent USB3.0Ѕ SATA3.0‫׬‬೚፣Ꮻ 2010ԑ7Т13Р

Agilent USB 3.0‫ד‬SATA 3.0༬⠛⧄࣪

Time

12:40~13:20 Registration & Demo Booth ‫ڜ‬൸଩ઝ‫ ݾ‬Agilent Technologies 13:20~13:25 Welcome & Opening 13:25~14:30 USB3.0 & SATA3.0 Update and Compliance Test Tips ‫ڜ‬൸଩ઝ‫ ݾ‬Agilent Technologies Tea Break & Demo Booths

14:30~14:45

14:45~15:15 USB3.0 solutions from ASMedia Technology

壁ጚઝ‫ ݾ‬ASMedia Technology, Inc.

15:15~15:45 The spirit of USB3.0

⢮໌ઝ‫ ݾ‬Etron Technology, Inc.

15:45~16:15 USB3ing Your Idea; Faraday's Solution

ཕ଺ઝ‫ ݾ‬Faraday Technology Corporation

16:15~16:25 16:25~16:55

Tea Break & Demo Booths GUC High Speed Interface IP Development & Implementation Experience

໌რሽ՗ Global Unichip Corp.

16:55~17:25 Texas Instruments & SuperSpeed USB

ᐚ‫ڠ‬Ꮪᕴ Texas Instruments

17:25~17:55 VIA Labs, the front runner of USB3.0!

৖ᔴሽ՗ VIA Labs, Inc.

17:55~18:00

Lucky Draw

USB3.0 & SATA3.0 Update and Compliance Test Tips

Francis Liu Senior Project Manager Agilent Technologies

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 1

SuperSpeed USB 3.0: PHY Electrical Testing

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 2

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Agilent Standards and Applications Program ‡ Our solutions are driven and supported by Agilent experts involved in international standards committees: ± Joint Electronic Devices Engineering Council (JEDEC) ± PCI Special Interest Group (PCI-SIG®)

± Video Electronics Standards Association (VESA) ± Serial ATA International Organization (SATA-IO) ± USB-Implementers Forum (USB-IF) ± Mobile Industry Processor Interface (MIPI) Alliance

± And many others ‡ :H¶UHDFWLYHLQVWDQGDUGVPHHWLQJVZRUNVKRSVSOXJIHVWVDQG seminars ‡ We get involved so you benefit with the right solutions when you need them USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 3

We understand your future requirements, because we help shape them

Rick Eads PCI-Sig Board Member

Jim Choate USB-IF Compliance Committee USB 3.0 Electrical Test Spec WG WiMedia CRB

Perry Keller JEDEC Board Member

Min-Jie Chong SATA 6G / PHY / LOGO Contributor SATA-IO Gold Suite Lead

Brian Fetz DisplayPort Phy CTS Editor VESA Board Member

The Agilent team maintains engagement in the top high tech standards organizations USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 4

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USB 3.0 Agenda USB-IF Compliance Program Status Physical Layer Overview

Transmitter Test Requirements Receiver Test requirements USB 3.0 Protocol Compliance Test Pitfalls Questions

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 5

Intro

USB Implementors Forum, inc (USB-IF)

USBIF Board Members Intel, NEC, HP, Microsoft, ST-Ericsson, LSI

OTG WG

CabCon WG

Compliance Review Board

Test Spec WG (Intel)

Compliance Committee influences

Agilent Active Membership

owner

USB2/USB 3 Tools and Test Procedures

USB Test Specs responsible

Device WG

owner

Marketing WG

influences

Test House Approval

Interop. Workshop Testing

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

1-3

SuperSpeed USB Timeline Broad Deployment Initial Deployment Product Development

STDs Development

???

USB 3.0 Electrical Compliance Test Specification 0.5

0.8

1.0 Test Spec

0.9RC

First USBIF certification event

USB 3.0 DevCon Taipei Apr 1-2

USB 3.0 Developers Conference: Tokyo May 20-21

USB 3.0 (FYI) Wksp: USB 3.0 (FYI) Wksp:USB 3.0 Taiwan/OR Feb 8-12 Wksp: April 26

T est L a b U SB 3 . 0 Qualificatio Wksp: n J ul 2 6 - 3 0

Compliance Program/Industry Enabling Development

2009

2010 USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 7

USB-IF Provides USB 3.0 Certification at Intel PIL ‡3,/RSHQHGLQ4¶

PIL is based at Intel OR, Hillsboro ‡All Scope vendor solutions are being evaluated at the PIL ‡Agilent has TX and RX test setups in PIL: '6$$DQG1%-%HUW%VROQ¶VZLWK SER option A02 ‡http://www.usb.org/developers/ssusb/ssusb_pil

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

1-4

What is different for USB 3.0 ‡USB 2.0 High-Speed

‡USB 3.0 SuperSpeed

9 480Mbps

95 Gbps

9 NRZI, Half Duplex

98B/10B PRBS, Full Simplex

9 4 signals

98 signals

Dp, Dm, VCC, GND

4 USB2 , 4 SS Signals

9 Cable Lmax= 5meter

9Cable Lmax= 3 meters

9 IconfigLP/FP = 100mA/500mA

9IconfigLP/FP = 150mA/900mA

9 Isuspend = 500uA

9Isuspend = 2.5mA

9 No SSC

9SSC

9 TX SQ at Near End

9TX at End of Channel (Far end)

9 No Host RX testing

9RX Jitter tolerance RX

Half Duplex TX

TX

Full Simplex TX

RX

RX

TX

RX

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 9

SuperSpeed Communication ± Physical Layer Focus Point to point communication, concurrent data flow Low power mode Link training Independent clock domains ± both using Spread Spectrum Clocking (SSC) NonSuper Speed

TX

TX

RX

RX

Super Speed

TX

RX

RX

TX

-or-

NonSuper Speed Super Speed

-or-

Transmitter (TX)

Cable / Channel

Receiver (RX)

‡ De-emphasis

‡ Backward compatible

‡ Equalization

‡ 8B/10B coding

‡ EMI requirements

‡ Clock recovery

‡ Data scrambling

‡ Signal integrity requirements

‡ Re-timing

‡ Insertion of Skip

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 10

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Transmitter test requirements

(TX Far End) USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 11

USB 3.0 PHY Electrical Test Specification ¾Key Updates ¾ RX compliance calibration and testing performed at end of the channel

¾ &KDQQHOGHILQLWLRQRIPHWHUFDEOHSOXV´WUDFHIRUKRVWDQG´ trace for Device ¾ Addition compliance Pj test points defined at 10Mhz, 20Mhz and 33Mhz ¾ TX testing will allow channel embedding

¾ Golden s-parameters selected for embedded test ¾ RX vertical stressed eye calibration set to 180mVp-p

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 12

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SuperSpeed Measurement Requirements

Transmitter Compliance Testing: 9&RPSOLDQFHZLOOEHPHDVXUHGDWWKHHQGRIWKH³FRPSOLDQFHFKDQQHO´ 9SMA termination for TX signals, phase matched SMA cable

9Terminate link under test with high speed oscilloscope 9Measure transmitted waveform with high speed oscilloscope 9Use compliance pattern 91M UI of data

9Compute: 9 eye diagram, 9 Rj from CP1 9 Dj, Tj@10^-12 BER from CP0 9 average data rate, 9 rise/fall time, 9 Test requirement for SSC Slew Rate 9 Test LFPS signaling USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

USB 3.0 Test fixture Key Features: ± Industries first and most feature complete ± SMA edge launch terminations ± SS A and SS B for host, device or cross hub testing ± Connect power supply or USB 2.0 port to pass through section to provide power to bus powered USB 3.0 products for ease of testing ‡ LED to indicate VBus is applied

± SMA breakouts for cross talk measurements of USB 2.0 to USB 3.0 or vice versa ± RX connections through JBert ISI board allows compliance channel emulation for pretesting ± Accurate fixture de-embed and compliance channel embedding is performed with VNA sparameter characterization and Agilent InfiniiSim toolset.

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 14 14

1-7

Additional USB 3.0 Tests: ‡ Automated LFPS timing measurements ‡ Test CP0 and CP1 jitter individually ‡ Automated test of Tj using CP0 and CP1 sequence per Draft test specification ‡ SSC parameter testing ‡Aux Out test control allows using scope to trigger sequential test modes USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 15

LFPS Test Requirements

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 16

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U7243A USB 3.0 TX Compliance Application

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 17

Tx testing emulated through s-parameters Embed Channel File ³DEVICE_3MCABLE.s4p´

Validation with InfiniiSim of DSA91304A USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 18

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Agilent S-SDUDPHWHUVQRZWKH³*ROGHQ &KDQQHO´IRU7;WHVWHPEHGGLQJ

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 19

U7243A Select Tests and Configure Tabs

Click All Tests and app will cycle through all test sequentially. Updated in 1.20 beta USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 20

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Agilent U7243A SW has built in compliance channel embedding

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 21

SuperSpeed Receiver Tests Spec. 1.0 Test Setup

‡Compliance Channels are used to test TX and RX for worst case channel conditions ‡Back panel USB route solution ‡Channel loss will dominate ‡+RVW´RIWUDFH ‡'HYLFH´RIWUDFH ‡3 meter USB 3.0 cable

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 22

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USBIF RX Compliance fixtures now DYDLODEOH«6RUWRI http://www.usb.org/developers/estoreinfo/

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 23

SuperSpeed Host Receiver Test Calibration and compliance channel

Host Channel setup USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 24

1-12

SuperSpeed Device Receiver Test Calibration and compliance channel

Device Channel setup

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 25

SuperSpeed Receiver Test Calibration and compliance channels

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 26

1-13

SuperSpeed Receiver Tests CTS 0.9RC Test Descriptions and Requirements Normative Receiver Tolerance Compliance Test ‡ ‡

TD.1.3: Loopback BERT Test TD.1.4: Receiver Jitter Tolerance Test

Jitter Tolerance Curve

Jitter Requirements -

Additional requirements ‡ Polling Loopback substate ‡ 5,000 ppm SSC

Periodic (sinusoidal) jitter frequencies 500 KHZ ± 50 MHz

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 27

SuperSpeed Receiver Tests Rx Compliance and Jitter Tolerance Testing

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 28

1-14

Receiver Test Procedure External Error Counter Turn on loopback by sending LFPS and required training sequences

The receiver stress pattern is BDAT with SKPs inserted as described in the standard. The pattern checker receives the looped stress pattern BDAT and recognizes bit errors After sufficient test time the error counter of the pattern checker is read Pattern Generator: J-BERT, ParBERT 2. . Pattern Generator

VWUHVVSDWWHUQ«

Pattern Checker Error Counter

1.

«VWUHVVSDWWHUQ«WUDLQLQJVHTXHQFHV«/)36

3.

Pattern Checker: USB Protocol Analyzer; Ellisys USB Explorer and NOW JBERTB SER USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 29

N5990A Valiframe Summary Test Automation Benefits Automated system calibration ± Ensuring high-quality compliance tests with calibrated jitter ± Enabling characterization and margin testing

‡ True RJ with high crest factor ± Worst-case stress for marginal devices ‡ Flexible characterization ± Arbitrary jitter mix, unique on-the-fly parameter variations ‡ Fully automated receiver tests ± Incl. loopback activation ‡ Multiple bus standards supported by main instruments ± Investment protection (USB, PCI Express, SATA, HDMI, DisplayPort, MIPI) ‡ Standard user interface and software framework ± Common user interface, test flow, results reporting across all applications ± Fast test execution ± Excel reporting, convenient data analysis and post-processing

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 30

1-15

NEW Agilent E5071C ENA Option TDR TDR Revolution

Engineered for USB3.0 Cable/Connector Designers

One-box Solution 3 Breakthroughs

for High Speed Serial Interconnect Analysis

for Signal Integrity Design and Verification

Time Domain

Frequency Domain

Simple & Intuitive Eye Diagram

Operation

Fast & Accurate Measurements E5071C ENA Series RF Network Analyzers ESD Robustness ESD protection inside

Method

Free

of Implementation (MOI)

Sample Program

USB3.0 Compliance Tests Support with Method of Implementation (MOI) and Free Sample Program USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 31

Recap ¾ Agilent is an active member of the USB 3.0 EWG working on the Test Specification and test methods for USB 3.0 ¾ U7243A integrates the Intel USB 3.0 SigTest tool for formal compliance testing ¾ USB3 requires testing at the end of the compliance channel: ¾ TX testing: basic embedding , RX testing requires testing with 3 meter cable plus ´´WUDFHIRU+RVW'HYLFHWHVWLQJ

¾ Agilent jBERT-B work with Opt. A02, SER/FER or Ellisys Explorer 280 USB 3.0 Protocol Analyzer ¾ Agilent offers the industries first USB 3.0 compliance Channel S-parameter ¾ Agilent's ENA option TDR is the fatest, accurate, ESD free for USB3.0 cable connector compliance, the MOI is available now

1-16

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 33

Agilent Contributes in SATA-IO IW Program ‡ Determine product compliance to the SATA specification

‡ Certification of products for SATA-IO Integrators List ‡ There are currently 3 physical layer GOLD suite test areas at Interoperability Workshops, as well as testing for cables Approved Agilent Method of Implementation Documents for SATA UTD 1.4 Physical Layer Transmitter

Physical Layer Receiver

Physical Layer Return Loss

Cable Test

Downloads are available from http://www.sata-io.org/developers/interop_14.asp USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 34

1-17

Agilent SATA and SAS Total Solution Coverage PHYSICAL LAYER Transmitter Characterization (PHY/TSG/OOB)

Receiver Characterization (RSG)

DSA91204A oscilloscope

N4903B Highperformance serial BERT

N5411B SATA and N5412 SAS compliance

BusXpert FER Counter

N8801A Protocol viewer software* ,QGXVWU\¶VORZHVWVFRSH noise floor/sensitivity and trigger jitter

PROTOCOL LAYER

Impedance/Return Loss (RX/TX)

N5990A Automated compliance and device characterization test Automated compliance software accurate, efficient, and consistent

Host/Device Digital (ASR, GTR, NCQ, SSP, IPM, DOF)

DCA 86100C Wideband sampling oscilloscope

U3052A BusXpert PRO Protocol Analyzer

54754A TDR/TDT module

U3051A BusXpert MicroLite Protocol Analyzer

86108A Precision waveform analyzer*

DCA ultra low jitter

Hardware with Native PHY and Fast Data Re-Lock. Software with Pre-Indexing, view any size trace in under 5 seconds USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 35

Physical Layer Test Parameters Tx, Rx Test - Impedance/Return Loss

PHY, TSG, OOB Test - Transmitter Signal Quality

RX-01 : Pair Differential Impedance RX-02 : Single-Ended Impedance (Obsolete) RX-03 : Gen2 Diff Mode Return Loss RX-04 : Gen2 Common Mode Return Loss RX-05 : Gen2 impedance Balance RX-06 : Gen1 Diff Mode Return Loss RX-07 : Gen3 Diff Mode Return Loss RX-08 : Gen3 impedance Balance TX-01 : Pair Differential Impedance TX-02 : Single-Ended Impedance (Obsolete) TX-03 : Gen2 Differential Mode Return Loss TX-04 : Gen2 Common Mode Return Loss TX-05 : Gen2 Impedance Balance TX-06 : Gen1 Differential Mode Return Loss TX-07 : Gen3 Differential Mode Return Loss TX-08 : Gen3 Impedance Balance

PHY-01 : Unit Interval PHY-02 : Frequency Long Term Stability PHY-03 : SSC Modulation Frequency PHY-04 : SSC Modulation Deviation TSG-01 : Differential Output Voltage TSG-02 : Rise/Fall Time TSG-03 : Differential Skew TSG-04 : AC Common Mode Voltage TSG-05 : Rise/Fall Imbalance TSG-06 : Amplitude Imbalance TSG-09 : Gen1 (1.5Gb/s) TJ TSG-10 : Gen1 (1.5Gb/s) DJ TSG-11 : Gen2 (3Gb/s) TJ TSG-12 : Gen2 (3Gb/s) TSG-13 : Gen3 (6Gb/s) Transmit Jitter TSG-14 : Gen3 (6Gb/s) Max Diff Vamp TSG-15 : Gen3 (6Gb/s) Min Diff Vamp TSG-16 : Gen3 (6Gb/s) AC Com Mode Voltage

RSG Test - Receiver Tolerance

OOB-01 : OOB Signal Detection Threshold OOB-02 : UI During OOB Signaling OOB-03 : COMINIT/RESET/WAKE Burst Length OOB-04 : COMINIT/RESET Transmit Gap Length OOB-05 : COMWAKE Transmit Gap Length OOB-06 : COMWAKE Gap Detection Windows OOB-07 : COMINIT/RESET Gap Detection Windows

RSG-01 : Gen1 (1.5Gb/s) Receiver Jitter Test RSG-02 : Gen2 (3Gb/s) Receiver Jitter Test RSG-03 : Gen3 (6Gb/s) Receiver Jitter Test RSG-05 : Receiver stress Test at +350ppm (Informative) RSG-06 : Receiver stress Test with SSC (Informative) USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 36

1-18

SATA Transmitter Test Requirements ‡ N5411B 6Gb/s transmitter compliance application for scope and 81134A pattern generator provides automated measurements for all 6Gb/s, 3Gb/s and 1.5Gb/s test parameters. ‡ Covers all the 3 transmitter test groups ± PHY, TSG and OOB. ‡ SATA Gen3 transmitter needs to meet the requirement for Gen2 and Gen1 (for backward compatibility). 81134A will work at 6Gb/s

SATA-IO Gold Suite Test Tool USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 37

SATA PUT Test Mode Requirements: BIST-L and BIST-TSA (PHY/TSG) BIST-L: Far End Retimed Loop Back (Spec Mandatory) 5HFHLYHSDWWHUQIURP33*DQGUHWUDQVPLWWKHVDPHSDWWHUQZLWK387¶VRZQFORFN

BIST-L

Required Test Pattern

Pulse Pattern Generator

010101

Rx

PUT Tx

010101

BIST-TSA&RQILJXUH387¶VWRWUDQVPLWUHTXLUHGWHVWSDWWHUQ Required Test Pattern

BIST-TSA T: Transmit Only (Even without Rx signal) S: Scramble Bypass (No scramble) A: ALIGN Bypass (No ALIGN primitives inserted)

PUT

Tx

010101

* PUT: Product Under Test (SATA term) USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 38

1-19

OOB Test Setup 81134A PPG Hand shake Emulation To DUT Rx

From DUT Tx Test Automation SW

Fixture

Scope

PUT

㽲 Connect PUT Rx to PPG output 㽳 Connect PUT Tx to Scope CH Input 㽴 Observe how PUT reacts to PPG signal USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 39

What is Jitter Transfer Function?

³-LWWHU)UHTUHVSRQVHRIWKH&'5´ Sweep SJ Freq with Fixed ABS ex. 0.3 UI value with JBERT Plot how much Jitter UIs observed on Scope Jitter analysis Jitter amplitude

Input Jitter

0.3UI

Measured Jitter on a Scope Jitter Frequency

Low Freq Jitter No Jitter seen. Tracked by CDR High Freq Jitter CDR cannot Track

dB

peaking

0dB -3dB

JTF: Measured Jitter/Input Jitter

30kHz

JTF

Jitter Frequency USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 40

1-20

Why Jitter Value vary by different setup ? ³%HFDXVHRIGLIIHUHQW-7)´

To resolve this issue, defined a JTF regulation range. ³8QLILHG-7)´ ³%HWWHU-LWWHU0HDVXUHPHQWFRUUHODWLRQ´(SATA-IO ECN#008) Jitter amplitude

JTF

Qualified JTF Measured Jitter

Jitter in ABS value Jitter Frequency

Jitter Frequency

Non Qualified JTF Measured Jitter Jitter Frequency

Agilent DSA90000A JTF

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 41

SAS Transmitter Test Requirements ‡ SAS-2 6Gbps Physical Layer Test Suite version 1.01 is written by UNH-IOL SAS Consortium. ‡ The transmitter test requirement consists of 3 test groups ± AC Coupling, TX SSC and TX NRZ Data Signaling Requirement. ‡ The SAS6G UDA transmitter compliance application for scope and provides automated measurements for all the following test parameters.

Source:ftp://ftp.iol.unh.edu/pub/sas/test_suite/SAS -2_6Gbps_Physical_Layer_Test_Suite_(v1.01).pdf N5421A SFF-8482 SAS x2 Test Fixture Kit USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 42

1-21

SAS TWDP Test SASWDP (Waveform Dispersion Penalty) code supplied by T10 committee is MatLab code TWDP: SNR degradation at the symbol decoder input due to ‡ Less-than-ideal transmitter waveforms ‡ Dispersion in the channel 9 The SASWDP Matlab script shows the WDP result to be 8.9dB is below the maximum spec limit of 13dB. 9 This measurement can performed using the SAS6G UDA. USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 43

SATA and SAS Receiver Jitter Tolerance Test My RX Receives without Error My RX Still Receives without Error How Good is My Rx ? How BAD signal could My Rx stand without error ?

Jitter injected Pattern Generator

CRC Error Counter

Jitter Tolerance Test = Verify How Good/Bad your Rx is. ³:KDW-LWWHUGLVWULEXWLRQGRHVP\5[ZRUNILQH"´ USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 44

1-22

How to create a Jitter Tolerance Curve 7RJHWD³&XUYH´QHHGWRWHVWD³3ODQH´

TJ [UI]

Pass Fail Compliance Test points Your Real Tolerance Point Jitter Tolerance Curve

SJ Frequency [Hz] Test time = Number of points* (How long to wait till Pass + Setup / load time)

Test with Matrix of Jitter value and Jitter Frequency and wait for Pass / Fail = MUST have Automated Testing and Quick Jitter setup/ load time

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 45

Receiver Setup using RF switch N4903A JBERT B

Optional Switch Trigger

N4915A-60001 ISI Channel + RX -

D-

BIST-L Source

+ TX -

TX

BIST L Source

Frame Error Counter

Product Under Test

N4915A-005 RF Switch

RX

Frame Error Counter

Test Adapter

D+

Framed COMP

D+ D-

Framed COMP

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 46

1-23

ValiFrame N5990A Test Automation Complete transmitter and receiver physical layer validation

DSO Oscilloscope

N5990A Automation Software

RJ and PJ

Switch

Pattern TX Generator

scra-

OOB & ³%,67/´ Source FER Counter

RX 10/8b mble TX

OOB detect retiming

RX

TX

Switch

8/10b

PUT

scramble

RX

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 47

RSG Application Details Excel Results RX Jitter Tolerance SATA 3.0 GBit/s Device 1000 900 800

Jitter [mUI]

700 600 Max Passed Jitter

500 400 300 200 100 0 1

10

100

Frequency [MHz]

Agilent RSG solution Sweeps QUICK ! ³6HWXS/RDGWLPH´LQ³PVRUGHU´

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 48

1-24

New J-BERT B Option A02 Calculates FER on 8B/10B Coded And Re-timed Data Streams ‡Handles flips in running disparity ‡Agnostic to insertion or removal of Aligns ‡Calculated BER is based on either 10B symbol errors or frame errors i.e. one wrong symbol/frame is assumed to be caused by a single bit error

USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 49

Summary ¾Superspeed product development proceeding rapidly ¾We work closely with early USB 3.0 product developers and USB 3.0 Contributors ¾ Test specification definition and verification ¾ Test procedures and compliance requirements

¾,QILQLL6LP³FRPSOLDQFHFKDQQHO´HPXODWLRQZLWKRXWUHTXLULQJWKHSK\VLFDO reference channel! ¾$JLOHQW¶V86%&RPSOLDQFHVROXWLRQOHYHUDJHVWKHHDVHRIXVHDFFXUDF\DQG automation delivered by USB 2.0, PCI Express and SATA applications.

¾Leading solutions adopted by test labs world wide (USB-IF PIL and workshop) ¾USB3.0 CTS is not final yet and change every month.

Agilent has the tools and expertise to help you succeed with USB 3.0 USB 3.0 & SATA 3.0 Technology Forum Agilent Technologies July 2010

Page 50

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USB3.0 Solution from ASMedia

ASMedia Technology Inc. Technical Marketing Dept. Chinyu Chang

Company Profile brief ƒ ƒ ƒ ƒ ƒ ƒ

Establishment : Mar. 2004 Capital : US$ 12.5 Millions Headquarter : Taipei, Taiwan Off shore offices : Shenzhen, Shanghai, China Employees : 120+ (engineer : 90% ) Core BusinessΚ ƒ Quick Switch and Repeater ƒ ƒ ƒ ƒ

PCI Express I/II/III, SATA-I/II/III, USB2.0/USB3.0, Display Port, HDMI, DVI and LVDS

ƒ Storage Controller ƒ ƒ ƒ

SATA, PATA, USB3.0 SSD Controller USB3.0 to SATA II/III, USB3.0 to NAND

ƒ PCI Express Bridge and Controller ƒ ƒ ƒ

USB2.0 / USB3.0, SATA I/II/III PCI

ASMedia Confidential Document

2-1

www.asmedia.com.tw

Background of ASMedia ƒ Over decades of design experience, key members are mostly chipset designers from Ali, SiS and VIA. ƒ Proven record and Capability to handle different IPs ƒ High speed interface : ƒ AGTL+, HT3, PCI-E I/II, SATA I/II/6G, 1394, USB2.0, PATA

ƒ Experience on S/W development ƒ includes BIOS, Driver, Firmware and rt-OS coding.

ƒ Production experience on ƒ various Process (from 0.5um~80nm), ƒ various Package (including TSOP, QFP, QFN, BGA, Flip-chip, MCM) ƒ over 10 millions/month chipset Business

ƒ In house equipment ƒ JBert and TDR and 90000 series scope from Agilent

ASMedia Confidential Document

SuperSpeed USB Features ƒ Up to 10x performance increase over USB2.0 ƒ Fast sync-n-go ƒ Minimizes user wait-time

ƒ Optimized power efficiency ƒ Provide excellent power characteristics both on the Device and the Platform ƒ U0/U1/U2/U3 support

ƒ Backward Compatible with USB2.0 ƒ Legacy devices continue to work in new host connector ƒ New devices work in legacy systems albeit at USB2.0 speed ƒ Existing class drivers continue to work

ƒ Same USB Device Model ƒ USB Framework ƒ Transfer types

ASMedia Confidential Document

2-2

Need for SuperSpeed USB ƒ Your Connectivity is Only As Fast As Your Memory ƒ Flash-based peripherals will require much higher data rates ƒ ƒ ƒ ƒ

Digital Cameras and Camcorders Flash Memory Drive (USB thumb sticks, and cards) Flash-based digital MP3 and video players PC, Mobile, Handheld PCs and Mobile phones

ƒ User wait time requirement, 1.5 min to synchronize ƒ Interface performance sets the requirement

ASMedia Confidential Document

comparison on Copy time, U3 v.s. U2 UFD Module run in USB3.0 port copy 1.36GB file in 27 secs

Regular Pen Drive run in USB2.0 port copy 1.36GB file In 3min 45sec

USB3.0 UFD with ASMedia solution Copy 1.36GB file ASMedia Confidential Document

2-3

USB2.0 UFD

ASMedia Switch Product Roadmap ASM1441A ASM1441B HDMI/DVI Switch

Video Switch

ASM1441ADP ASM1441BDP DP Switch

ASM1445 1:2/2:1 Switch 3.3V HDMI/DVI

ASM1452 LVDS Switch

ASM1443 1:2/2:1 Switch with Level Shifter

ASM1442T ASM1442

Repeater

High speed signal switch for PCIe/SATA/USB3.0

HDMI/DVI Level Shifter

ASM1456 SATA 6G Switch

Interface Switch

ASM1455

ASM1458

PCIe/USB3.0 Switch

USB3.0/USB2.0 Switch

ASM1440 ASM1430 PCIe Gen2 Switch

ASM1453

ASM1450

SATA-II Switch

USB2.0 Switch

MP Now

Q4’10

Q3’10

ASMedia Confidential Document

ASMedia Storage Product Roadmap

ASM1051/L/U/E

ASM1052/E

ASM1051A

USB3.0 / eSATA to SATA

USB3.0 to SATA

USB3.0 to SATA

ASM1030 USB3.0 Pen Drive

1st MP in the world

ASM2053 USB3.0 / SATA 6G SSD

ASM2042 ASM2041P/42P SATA/PATA SSD

MP

Q3’10

Q4’10

ASMedia Confidential Document

2-4

Q1’11

Q2’11

ASMedia PCI Express Controller Roadmap ASM1062R ASM1062 PCIe to 2S1P SATA 6G

SATA PATA

SATA 6G HW RAID

P2P

ASM1060 PCIe to 2S1P SATA 3G

P2P

ASM1042

USB3.0

PCIe to 2*USB3.0

ASM1083 PCIe to 2*PCI

PCI ASM1085 PCIe to 5*PCI

MP

Q3’10

Q4’10

H1’11

ASMedia Confidential Document

USB3.0 Logo for ASM1051 series product

ASMedia Confidential Document

2-5

Passed USB 2.0 and SATA-IO compliance test

ASMedia Confidential Document

ASM1051 series Performance Test

USB2.0

USB3.0 Device USB3.0 to SATA ASM1051/E ASM1051U

+ Mother board

+

NEC USB3.0 Host ( PCIeX1 Gen2 )

SSD

ASM1051 with X-25E SSD

ASM1051E with SATA6G SSD

ASM1051U with UAS

USB3.0 to SATA-II

USB3.0 to SATA-III

4K R/W with Queue

ASMedia Confidential Document

2-6

ASM1042 Performance Test ASM1051E USB3.0 to SATA 6G

+

+ Mother board

ASM1051E

USB3.0 host ( PCIeX1 Gen2 )

+ SATA 6G SSD

ASM1042 USB3.0 Host 356 MB/s for Read 229 MB/s for Write

Other Host

ASMedia Confidential Document

Summary ƒ

Provide high performance Signal Switch for Interface and Video solution

ƒ

Provide Re-driver chips for SATA gen2/3 and USB 3.0 for Long PCB routing trace and Daughter Card design

ƒ

Provide high-Speed Storage Solution for USB 3.0 series ƒ ƒ ƒ ƒ ƒ

ƒ

Enclosure for HDD/SSD/ODD UFD with ONFI and legacy flash support up to 2x nm process Card reader with SDXC Hub up to 4 ports Video/audio applications

Provide next generation High-Speed I/O controller solution for PC/NB ƒ ASM1042 : PCIe to x 2 USB3.0 Controller ƒ ASM1062 : PCIe to x 2 SATA 6G and PATA Controller ƒ ASM1085 : PCIe to x 5 PCI Bridge

ƒ

Best Partner in High-Speed I/O solution

ASMedia Confidential Document

2-7

Thank You !!

ASMedia Confidential Document

2-8

Stacked Die Enabler

Etron Technology, Inc. Since 1991

The spirit of USB 3.0 by

Chien-cheng Kuo Director System IC R&D Div.

Stacked Die Enabler

Safe Harbor Notice This following presentation contains forward-looking statements, which involve known and unknown risks and are subject to uncertainties that could cause actual performance, financial results, or operation conditions to be materially different from those contained in the forward-looking statements. Except as required by law, we undertake no obligation to update any forward-looking statement, whether as result of new information, future events, or otherwise.

3-1

Stacked Die Enabler

Agenda „ USB History „ The success of USB „ USB host controller „ The spirit of USB 3.0 „ About Etron

Stacked Die Enabler

USB History

3-2

Stacked Die Enabler

USB 1.1 „ Universal Serial Bus for peripheral device        

UNIVERSAL Hot-plug and unplug Serial and differential wired Bus Multiple transfer type (CONTROL/BULK/INT/ISOC) Simple design/low power Full-speed: 12Mbps Low-speed: 1.5Mbps 3.3V signal amplitude

Stacked Die Enabler

USB 2.0 „ High-speed: 480Mbps „ Same form factor and same pin count „ Backward compatibility    

Protocol layer Transfer type Class driver Application

„ Smaller signal amplitude: 400mV „ SPLIT transaction for FS/LS

3-3

Stacked Die Enabler

USB 3.0 „ SuperSpeed: 5.0Gbps „ Dual-simplex, 4-wire differential signaling „ Link power management „ Backward compatibility  Protocol layer O

ERDY/NRDY flow control

 Transfer type O

BULK has stream capability

 Class driver  Application

Stacked Die Enabler

The success of USB „ USB 1.1       

Hot-plug and play All ports are the same Class specification Low cost/Low power design Bus power max 500mA Increase ports by Hub Good user experience

3-4

Stacked Die Enabler

The success of USB „ USB 2.0  Higher bandwidth  Backward compatibility O O

USB 1.1 host controller/Hub USB 2.0 device USB 2.0 host controller/Hub USB 1.1 device

 Same connector  Same class driver  Same user experience

Stacked Die Enabler

The success of USB „ USB 3.0?  More Higher bandwidth  New features O O

ERDY/NRDY flow control Stream

 Backward compatibility  Same class driver  Same user experience

3-5

Stacked Die Enabler

USB host controller „ The role of host controller in USB system      

Host directed transaction The root of tree-like topology Bridge between Host system and device All speeds backward compatibility Fair access policy for every endpoints Performance/power management O O O

Bandwidth is shared by all the ports of one host controller Port suspend or Global suspend Balance between performance and power

Stacked Die Enabler

USB 1.1 host controller „ UHCI & OHCI  Support FS/LS devices  USB controllers are bus-masters and access memory-based schedules O O

Host controller driver create schedules Move data between memory and USB bus by DMA

 Root Hub/Root Ports O O O

Plug & unplug detection FS/LS detection Port suspend/resume

3-6

Stacked Die Enabler

USB 2.0 host controller „ Companion host controllers  OHCI or UHCI  Support USB 1.1

„ EHCI  Support HS devices  Bus-masters and access memory-based schedules  Root Hub/Root Ports O O

O

Plug & unplug detection Port routing logic to route port to the host controller who owns this port Port suspend/Resume

Stacked Die Enabler

USB 2.0 system block diagram Client Driver Software Universal Bus Driver (USBD)

USB 1.1 compatibility is guaranteed by companion HC & driver

Companion (UHCI or OHCI) Host controller Driver

Enhanced Host Controller Driver (EHCD)

Companion (UHCI or OHCI) Host controller

Enhanced Host Controller (EHCI)

Port routing logic

USB device

3-7

Stacked Die Enabler

USB 3.0 host controller „ xHCI  No companion host controller O O

Support different speeds by Bus Instance (BI) SS BI, HS BI, FS/LS BI

 Support SS/HS/FS/LS devices  Schedule is controlled by host controller  Root Hub/Root Ports O O O

Plug & unplug detection SS Link control Port routing logic

Stacked Die Enabler

USB 3.0 system block diagram Application Software Application Software Application Software

Class driver

Class driver

Universal Bus Driver (USBD) eXtensible Host Controller Driver (xHCD)

eXtensible Host Controller (xHC)

FS/LS Bus Instances

HS Bus Instances

SS Bus Instances

Root Hub/Root Ports

USB device

3-8

Stacked Die Enabler

The challenges of USB 3.0 host controller „ USB 2.0 backward compatibility  No companion host controller and driver

„ SuperSpeed Bus Instance  Performance/Power balance  SuperSpeed electrical compliance

„ Schedule control  Fair access policy for every endpoints

„ Driver (xHCD)  USB2.0 support and SuperSpeed support  New features support O O

Stream UASP

Stacked Die Enabler

The spirit of USB 3.0 „ The USB 3.0 host controller plays an very important role for USB 3.0  USB 3.0 host controller includes xHCI compliant host controller and xHCD driver

„ Etron USB 3.0 host controller ± EJ168  Complies with USB 3.0 specification revision 1.0  Complies with eXtensible Host Controller Interface (xHCI) specification revision 0.96  PCIe Gen2 x1 lane for host system  Two USB 3.0 downstream ports provide SS/HS/FS/LS signals

3-9

Stacked Die Enabler

EJ168 ± block diagram Universal Bus Driver (USBD) Etron eXtensible Host Controller Driver (xHCD)

Etron EJ168 EJ168 total solution

DMA

DMA

DMA

FS/LS Bus Instances

HS Bus Instances

SS Bus Instances

HS/FS/LS Root Hub/Root Ports Two High-Speed/ Full-Speed/LowSpeed Ports

SS Root Hub/ Root Ports

Two SuperSpeed Ports

Stacked Die Enabler

EJ168 ± USB 3.0 host controller „ Three independent Bus Instance for FS/LS, HS and SS  Optimized for different speeds  Synchronized frame interval between BIs  Fully adapted the advantages of xHCI on FS/LS and HS BI O O O O O

Not EHCI/OHCI with wrapper No USB2.0 Hub integrated Full 480Mbps bandwidth for HS devices Full 12Mbps bandwidth for FS/LS devices Lower CPU utilization

3-10

Stacked Die Enabler

EJ168 ± High-speed performance

The test results will vary based on the system or device used

Stacked Die Enabler

EJ168 ± SuperSpeed performance

The test results will vary based on the system or device used

3-11

Stacked Die Enabler

Etron xHCI host controller driver

Stacked Die Enabler

Etron Technology, Inc. (Ticker: 5351.TW) „ Fabless IC Design House since 1991 „ IPO in Taiwan Stock Market, 1998 „ 0DUNHW&DS$VVHW6KDUHKROGHU¶V(TXLW\ US$365M / 308M / 190M „ Employee: 458 „ Patents: USA/Total 102/223 „ Headquarters: Hsinchu Science Park „ Branch Offices & Liaison

Pacific Ocean Headquarters

 USA : Santa Clara, Boston  China : HK, Shanghai, Shenzhen  Japan : Tokyo

Etron „ Ranked 9th DRAM Supplier Worldwide „ Ranked 1st Fabless DRAM Supplier Worldwide „ The Pioneer in Application-Driven Memories (ADM) and Known-Good-Die Memories (KGDM)

3-12

Stacked Die Enabler

Revenues by Year NT$M 14,000 12,000

403 13,219

US$M

322

NT$M

10,481

10,000

189

8,000 6,000 4,000

128 109 3,405

80

6,331

207 6,705

88 4,402

241 222 7,560 7,297

As of May

129 4,102

2,713 3,056

2,000 0 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010

Stacked Die Enabler

Thanks!

3-13

USB3ing Your Idea; )DUDGD\¶V6ROXWLRQV Faraday Technology Corporation James Yang July 13,2010

Table of Contents 1

:K\)DUDGD\¶V86%"

2

What do we have now ?

3

PHY test results

4

Summary

2

Excel Your Idea to Silicon

4-1

Faraday, Pioneer & Leader in USB3 ™ We Faraday have devoted ourselves to the solution development in USB3 since early 2009 ™ The solution includes PHY in various technologies, device controller, OTG controller (under design) and turnkey service ™ Deliver the fastest realization of your idea in any USB3 application

3

Excel Your Idea to Silicon

USB3 Forecast 2011: 250Mu 2012: 700Mu

4

Excel Your Idea to Silicon

4-2

Why Faraday ? Compatibility & Logo ™ Compliance with hosts products ™ Hosts: Major host providers keep on delivering chips to the end products such as dongles, add-on cards, motherboards and notebooks, etc, as shown in the current market. The ubiquity of USB3 hosts will be foreseen in this year ™ Compatibility : With strong partnership with the host provider, Faraday can guarantee the seamless connection with all the host products

™ Logo ™ )DUDGD\¶VKRVW GHYLFHFXVWRPHUVKDYHJRWWHQ6XSHU6SHHGORJRV from USB PIL with the latest compliance version

5

Excel Your Idea to Silicon

Why Faraday ? Completeness & Reliability ™ USB2.0 leverage ™ Faraday has shipped over 200M USB2.0 units totally, always play as the key USB solution provider in the world for fulfilling customers requirement in compatibility and time to market

™ Not only USB ™ Other high speed interfaces : SATA, PCIe, Ethernet, DDRI/II/III, Serdes, etc. ™ 32-b ARM-compatible CPU ™ The other analog IP such as ADC, DAC, regulator, PLL, and cell library, memory

™ Experienced integration and back-end capability ™ Offer customers the thorough solution and plentiful combination 6

Excel Your Idea to Silicon

4-3

Block Diagram of PHY Control Registers

I2C I/F

8b/10b Encoder

Tx

M U X

Pattern Generator PIPE

Tx Driver

P2S

SSTXP SSTXM

SSCG

PIPE Interface Pattern Checker LFPS Detector

M U X

8b/10b Decoder

Rx

Tx State Machine

M U X

Elastic Buffer

Bit Stuffer

NRZI Encoder

M U X

S2P

Rx Receiver

SSRXP SSRXM

Tx Driver

P2S

Pattern Generator UTMI

UTMI Interface

DP DM

Pattern Checker

Rx State Machine

NRZI Decoder

Bit Unstuffer

PCS

Data Recovery

Rx Receiver

S2P PMA

7

Excel Your Idea to Silicon

Brief of PHY Features ™ Fully compliant with SuperSpeed, high-speed, full-speed, and low-speed electrical specifications. ™ Compliant with PIPE v3.0 and UTMI+ v1.0 for easy integration ™ Supports all USB 3.0 power saving modes (U0, U1, U2, and U3) ™ Generates clock ranging from 30 /12 /10 MHz source using either crystal or external source ™ Adaptive receive equalization mitigates signal attenuation due to the channel and crosstalk noises ™ Programmable transmitter amplitude for low power and deemphasis level ™ Supports spread spectrum clock generations to reduce EMI ™ Self-calibrated termination resistance

8

Excel Your Idea to Silicon

4-4

Block Diagram of Controller

9

Excel Your Idea to Silicon

Brief of Device Controller Features ™ Same programming model for SS, HS, FS ™ Shares the registers in USB2 and USB3 ™ Support internal DMA, but DMA can be hardware defined or disabled ™ Support LPM in USB2 and U0, U1, U2 & U3 in USB3 ™ Support programmable FIFO memory allocation for per EP ™ Programmable non-EP0 FIFO sizes of 1K bytes ~ 16K in USB3, and programmable non-EP0 FIFO size aligned with the max packet size in USB2 ™ Support EP0 FIFO sizes that configured with any powers of %\WH%\WH« ™ EP0 USB commands handled by software ™ USB bus level and packet level errors handled by hardware ™ AHB bus supported with programmable burst types and wrapper to AXI and other CPU interfaces

10

Excel Your Idea to Silicon

4-5

EVB1 : PHY Daughter Board

PIPE & UTMI interface

Power jumper Setting switch

Power jumper Power jumper Excel Your Idea to Silicon

USB 3.0 PHY test chip

Power jacket and switch 11

EVB2: SoC with 32-b RISC CPU Test chip of FIE33369 general purpose SoC platform

PIPE interface socket PIPE interface socket

USB 3.0 PHY test chip USB 3.0 device controller in FPGA 12

Excel Your Idea to Silicon

4-6

EVB2: Block diagram of SoC System AHB bus

PIPE FPGA

USB 3.0 PHY

FIE3369 test chip

USB 3.0 cable DDRII DRAM

13

Excel Your Idea to Silicon

LFPS - 1

14

Excel Your Idea to Silicon

4-7

LFPS - 2

tBurst

tRepeat 15

Excel Your Idea to Silicon

SSC - 1

16

Excel Your Idea to Silicon

4-8

Eye Diagram - 1

17

Excel Your Idea to Silicon

Jitter Tolerance - 1

18

Excel Your Idea to Silicon

4-9

Jitter Tolerance - 2

19

Excel Your Idea to Silicon

Summary ™ Faraday provides the complete PHY and controller solutions to USB3-interested customers, ™ The major advantages are: ™ Low power ™ Low BOM ™ High margin ™ Compliance

™ Not only in USB3, the other digital and analog IPs are also proven for the optimized architecture ™ (YDOXDWLRQERDUGVDUHUHDG\IRUFXVWRPHUV¶IDVW performance evaluation and system development ™ Please contact Faraday Technology Corporation for further information 20

Excel Your Idea to Silicon

4-10

High Speed Interface IP Development & Implementation Experience

໌რሽ՗ Stanley Huang 7/13/2010

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

Global Unichip Corp. Confidential Security C

What is SerDes ? A SerDes or serializer/deserializer is an integrated circuit transceiver that converts parallel data to serial data and vice-versa The transmitter section is a parallel-to-serial converter The receiver section is a serial-to-parallel converter The PLL is used to keep time for serializer/ deserializer pair

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

5-1

1

General SerDes Architecture

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

2

SerDes Applications SerDes are used in computing, storage, networking, and fiber optic communications PCI Express Gen1/Gen2/Gen3(2.5/5/8Gbps) USB3 (5Gbps) SATA Gen1/Gen2/Gen3 (1.5/3/6Gbps) Fiber channel (1.0625/2.125/4.25/8.5Gbps) Gigabit Ethernet (1.25Gbps) XAUI (3.125/6.25Gbps) 10G Base-R/XFI (10.3125Gbps) FTTH/xPON OIF CEI 6G-SR/LR (up to 6.375Gbps)

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

5-2

3

Common SerDes Examples

SAS (Serial SCSI)

XAUI GUC Confidential & Proprietary

10G

Fiber Channel

Copyright © 2010 All rights reserved

4

High Speed SerDes Advantages Bandwidth/pin can be increased by switching from a parallel interface to a higher speed serial interface Expandable by using Parallel Lanes Extendable to future generations while supporting legacy speeds/protocol Power/Ground noise is reduced. With differential current switching drivers, dI/dt on supplies is small New Interfaces can abandon legacy and plan for future processes. Removes voltage tolerance requirement ± eg. ATA to SATA, PCI to PCI-e, AGP to PCI-e, LPC to USB Point to Point, Dual Termination Busses result in relatively quiet system bus interfaces

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

5-3

5

Typical SerDes Characterization Equipment Agilent J-BERT N4903A Agilent Infiniium DCA-J Oscilloscope 86100C Agilent Pattern Generator 81133A

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

6

11.2 Gbps TX Eye Diagram (PRBS31)

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

5-4

7

PLL Jitter @ 10.3125GHz No filtering and including trigger jitter

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

8

RX Jitter Generation @ 10.3125Gb/s

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

5-5

9

XFI Jitter Tolerance (Jitter Injection) XFI Jitter Injection Setting : ± ISI = 0.2UI ± RJ = 0.2UI (pk-pk @ 1e-12) ± BUJ = 0.25UI ± Total = 0.65UI + Sine.Jitter

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

10

Jitter Tolerance @ 11Gb/s Preliminary Data: XFI compliant with at least 20% margin. Characterization & fine-tuning on-going.

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

5-6

11

Professional Verification & Test Solution Chip-Package-Board Co-Design Test Solution Serial bus Memory interface

Chip Package

+

Board

Test Solution

Æ

1st-Silicon Success Production Proven Flow Yield Excellence

Co-Design

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

12

Chip-Package-Board Co-Design For I/O Improve performance Eye diagram, jitter, SSO push out, noise, crosstalk

Reduce cost Lower package & PCB layer count, reduce decap on chip/PKG/PCB Chip model

Package model

+

Board model

+

Æ GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

5-7

13

I/O Simulation: Si + Package + Board S i M odel

Package Model

Bump

Tx

Trace

Bump

P CB Trace

BGA &

P TH

& via

Rx

Channel Model

V ia

Trace

P CB Trace

BGA &

P TH

& via

V ia

C ap

Connector

Daughter Card

P CB Trace

C a b le

Connector

HSPICE GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

14

SerDes and DDR DFT SERDES production solution

On-board DDR at speed test

CP : Internal loopback

Simply DDR traces toggling patterns

Build in BIST circuitry in ASIC

FT : External loopback Pattern Generator

DDR

Serializer

CHIP

.. Digital Far-End Loopback

Near-End Analog Int. Loopback

Near-End Analog Ext. Loopback

Pattern Analyzer

..

De-Serializer

GUC Confidential & Proprietary

CDR

Copyright © 2010 All rights reserved

5-8

CHIP DD R

CH IP

15

GUC IP Solution SerDes Test Setup & Equipment

EVB Evaluation Board

Sampling Scope

J-BERT Test Equipment

Protocol Analyzer

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

16

GUC IP Solution Overview Comprehensive IP solution GUC plus strong partnership with TSMC, Synopsys, ARM, Denali and more

Professional integration and mass production know-how PCI-E, SATA, XAUI, USB, SerDes, DDR Proven IP sourcing, Packaging effect, Domain IP test

Efficient customer support infrastructure FAE on-site support, CAE to ensure IP smooth mass production, experienced analog team for IP customization

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

5-9

17

Thank you !

www.globalunichip.com

GUC Confidential & Proprietary

Copyright © 2010 All rights reserved

5-10

18

Andy Lin Interface & Clock Products ASIA Business Development Manager

TI offers wide range of USB-IF certified silicon: Stand alone USB solutions, including hubs, peripherals, OTG, transceivers, signal switches, and power management devices USB enabled SoC DSP/OMAP solutions USB IP for core ASIC

TI has the support tools, software, documentation, and systems expertise to help simplify design and speed time to market. TI has a long standing presence in the USB-IF with involvement in many working groups including (not limited to) USB 1.x, USB 2.0, SuperSpeed USB 3.0 On-The-Go, ULPI, Certified WUSB, USB Charger, High–Speed Interchip

TI is actively involved in USB DWG activities: UASP WG OTG WG Battery Charging WG USB audio WG Video Display WG

6-1

TI/Intel co-defined USB 3.0 requirements prior to founding of Promoter’s Group Feasibility study of existing cable/connectors, Electrical Requirements, and Market Requirements Document

Active member of the USB 3.0 promoter’s group 6 Promoters and over 180 Contributors 27 TI employees active in the USB 3.0 technical working groups Electrical, link layer, protocol layer, power management, and hub specifications

TI USB 3.0 Development Leadership Mixed-Signal Development Expertise (Analog & Digital) SW Development Expertise (Driver & Firmware) FPGA Development Expertise to enable early SW Development Platforms 65nm PHY Development (First Silicon Mar 2009) TUSB1310 (Discrete PHY) sampling today ARM Cortex M3 Processor Subsystem for Device Controller Applications TUSB9260 (SATA Bridge) sampling today Broadest 2010 Roadmap (Discrete PHY, SATA Bridge, Hub, and Host Controller)

USB SuperSpeed 3.0 Overview

6-2

Data rate extended to 5Gbps from 480Mbps Separate Tx & Rx Channels Leverages PCI Express Gen II electricals Optimized Power Efficiency

USB 3.0 is the next evolution of the most popular and successful PC interface of all time. The USB 3.0 Promoter’s Group consists of HP, Intel, Microsoft, NEC, NXP, and TI. Fast Sync-N-Go

No device polling Lower active & idle power requirements

Minimizes User Wait-Time Download 27 GB HD movie in 60-70 sec

Specification released on Nov. 14, 2008. First silicon should be available in late 2009 with early production in 2010.

Backward compatible with USB 2.0 “to the User” Devices interoperate with USB 2.0 platforms Hosts support USB 2.0 legacy devices

For more information about USB 3.0 and how to become an Adopter go to www.usb.org/developers

SuperSpeed USB Highlights Next evolution of the wired USB Interface Data rate extended to 5.0 Gbps from 480Mbps Separate Tx & Rx Channels (Full Duplex vs. Half Duplex)

USB 3.0 Version 1.0 Specification ratified Nov. 2008 Lower Power per Bit Transferred 1/3 Power of USB HS for equivalent data payloads ~10% transmission duration at 3X peak power

Backwards compatible via cable/connector strategy

6-3

The Need for USB 3.0

Technology Cell Phone Node 2GB 44 min USB 1.1 1.1 min USB 2.0 6.6 sec USB 3.0

iPOD/MP3 4GB 1.5 hrs 2.1 min 12.2 sec

Digital Camera 8GB 3.0 hrs 4.2 min 24.4 sec

HD Camcorder HD Video Ext Storage 16GB 25GB 500GB 5.9 hrs 9.3 hr 7.9 days 8.9 min 13.9 min 4.5 hrs 53.3 sec 70 sec 26.1 min

USB 3.0 Value Proposition • The need for Data Transfer • Content sharing between Handheld Devices, PC’s, and Portable Devices • Content sharing between Friends & Family • Data Backup and Protection • Large File Sizes • Rich File Content (i.e. – file sizes growing rapidly) • Exploding HDD and Flash Sizes makes it “easy” to backup entire data libraries cost effectively • Transfer Time enables Applications & Markets • Walmart Study – Consumer patience is less than 2 minutes for data transfer

7

WW USB Market Shipments Wired USB Market Growth (InStat - July 2009) 4,500,000

> 1.25 Bu > 700Mu

4,000,000 > 300Mu

3,500,000 3,000,000 2,500,000 2,000,000 1,500,000 1,000,000 500,000 0 2007

2008

2009

2010

Full-Speed & Low-Speed

2011

High Speed

2012

2013

SuperSpeed

• USB 3 (SuperSpeed) Product launch begins late 2009-2010 • Anticipated Catalog Products by 2010 • Host Controller, SATA Bridge, PHY, Hub, and Flash Bridge • USB 3 volume shipments exceed 0.5-1.0Bu/yr by 2012-13

6-4

Benefits of USB SuperSpeed to Market • Ubiquitous Interface • Most prevalent interface within the electronics industry (Recognition by Consumers WW) • Backwards Compatible • Cable/Connector methodology enables SuperSpeed devices to interface with legacy High Speed devices • Improved bandwidth/efficiency • High Speed = Half Duplex • SuperSpeed = Full Duplex (1/3 Power to Transmit Data) • Multiple Use Port (Saves valuable real estate) • Power/Charging (SuperSpeed = 900mA vs. High Speed = 500mA) • Data Transfer (SuperSpeed = 5.0 Gbps vs. High Speed = 480 Mbps) • Video Output Port • SuperSpeed Video Work Group specification under way • Potential “Killer Applications” enabled by USB SuperSpeed

The goal is for most Sync-n-Go operations to take less than 90 seconds, which seems to be the “threshold of pain” for many end-users. The Table below summarizes the user experience enhancement in moving from USB full-speed to USB high-speed, and then up to SuperSpeed USB. Song or Picture

256M Flash Drive

Typical File Size

4 MB

256 MB

USB Full-speed

5.3 sec

5.7 min

USB High-speed

0.1 sec

8.5 sec

SuperSpeed USB

0.01 sec

0.8 sec

1G Flash Drive

Standard Definition Movie

16G Flash Drive

High Definition Movie

1 GB

6 GB

16 GB

25 GB

22 min

2.2 hr

5.9 hr

9.3 hr

33 sec

3.3 min

8.9 min

13.9 min

3.3 sec

20 sec

53.3 sec

70 sec

As you can see, SuperSpeed USB will enable user experience of well under 90 seconds for all the listed Sync-n-Go applications. Another way to think about this is to consider how much data you can move in that target 90 seconds. Table 2 summarizes some key applications:

Songs/Pictures (4MB/files)

Standard Definition Movie (6 GB/file)

High Definition Movie (25 GB/file)

USB High-speed*

~ 675

< 50% of a movie

1 entire movie

* Assumed actual data through put of 25MB/sec which is typical of most USB High-speed Systems ** Assume a minimum data throughput of 300MB/s – the goal of the SuperSpeed USB development effort for mass storage applications

6-5

New and emerging applications will benefit from higher performance while USB 2.0 is adequate for many applications. SuperSpeed USB provides bandwidth and performance for flash-based, content-rich portable devices. Rich content is increasing in size demanding an increase in storage capacity Market Adoption Early Adoption (Late 2009 – Mid 2010)

Enabled by discrete SuperSpeed USB xHCI host controller based on PCI-E Gen2 embedded solution Target Add-on Card market and mother board Broad Deployment (mid 2010 & beyond)

Enable by embedded SuperSpeed USB xHCI host controller chip set Initial target is high-end desktop and broader market adoption with cost effective solution.

Hub Controllers

Peripherals

Transceivers

Hosts / On-the-Go

TUSB2036

TUSB3210

TUSB1105/1106

TUSB6020

USB Full-speed 2/3-Port Configurable

USB Full-speed General Purpose 8052 MCU

USB Full-speed NXP Drop-in Replacement

USB High-speed OTG VLYNQ Local Bus Interface

TUSB2046B

TUSB3410

TUSB2551A

USB Full-speed 4-Port

USB Full-speed Programmable USB-to-Serial Bridge

USB Full-speed Micrel Drop-in Replacement

TUSB2077A

TUSB6250

USB Full-speed 7-Port

USB High-speed Programmable USB-to-IDE Bridge

TUSB2136 Compound USB Full-speed 2-port with General Purpose 8052 MCU

TUSB7340 – 4 Port USB 3.0 Super-speed xHCI

TUSB1210

TUSB7320 – 2 Port

ULPI PHY

USB 3.0 Super-speed xHCI

TUSB9260

TUSB1211

USB 3.0 Super-speed to SATA(HDD)

ULPI PHY w/ Charger Detection

TUSB8040

TUSB1310

USB 3.0 Super-speed 4–port Hub

USB 3.0 Super-speed Transceiver

TUSB8030

Re–Driver

USB 3.0 Super-speed 3–port Hub

Sampling

SN65LVPE502 Single Lane USB 3.0 Re-Driver w/ EQ

TUSB8240

In Development

USB 3.0 Super-speed 2–port Hub

ESD TPD2EUSB30

New Release

2–Channel High Speed ESD

In Production

6-6

Two–level Equalization Control Nine–level De-emphasis Control 400mW max power (Vcc=3.6V)

Makes bad signals good again Flexible signal conditioning for different media Low power Up to 24 inches of 6 mil on FR4 Save board space Protection against transients