2nd DAC EDA Roadmap Workshop June 14, 2010, 9am – 3pm Anaheim Convention Center, Room 213D
For latest version, contact J. Antonio Carballo (
[email protected]) or Andrew Kahng (
[email protected])
Goals Goal of this workshop –To further the dialogue between the various communities / bodies involved in roadmapping design technology, and to bring together key constituencies (designers, EDA companies, researchers, and multiple world regions) with a view towards a more explicit future interlock Uniqueness of this workshop –The only forum for deep discussion around roadmap issues related to the EDA industry. Leaders from semiconductor companies, consortia, and academia jointly assess the need for and state of roadmap efforts, to craft a blank-sheet view of roadmap activities for the next 15 years TODAY Where/How should the EDA industry improve its roadmap(ping)? 1
Our Agenda ! Session/title
Speaker(s)
Time
Introduction and Plenary
J.A.Carballo (IBM), A.B. Kahng (UCSD)
9AM
Session I: Corporate Roadmap Views IBM's EDA Roadmap View
David Kung (IBM)
9:20
IDM View
Shishpal Rawat (Intel)
9:40
EDA Standards @ Si2: 2010 view
Sumit Dasgupta (Si2 Roadmap)
10:00
GF EDA Roadmap View
Walter Ng (GlobalFoundries)
10:20
EDA 360
Andreas Kuehlmann (Cadence)
10:40
Maximizing performance per Watt
Rob Knoth (Magma)
11:00
IP View
Yervant Zorian (Virage Logic)
11:20
IDM / Fablite View
Nagaraj NS (TI)
11:40
Panel Discussion and Working Lunch (sandwich orders in the morning)
Noon
Session II: Consortia (and Corporate Stragglers) Views EU CATRENE / ENIAC roadmap
Ahmed Jerraya (CEA-LETI)
1:10
Japan's EDA Roadmap View
STRJ (Kahng / Carballo rep)
1:30
ITRS's EDA Roadmap View
Kahng / Carballo (UCSD / IBM)
1:50
IP View
Dipesh Patel (ARM)
2:10
Panel Discussion and Next Steps
Kahng / Carballo (UCSD / IBM)
2:30
Some Questions and Actions from 2009 QUESTIONS 1. What would make an EDA roadmap more useful ? – To whom ? (R&D, marketing, standards bodies, consortia, ...) 2. Which EDA areas lack most in roadmap efforts – Parallel EDA, SW EDA, analog EDA, ESL ? 3. Which EDA areas are behind what the roadmaps say ? –
Does this matter ?
ACTIONS 4. Need: Process to ensure tight contributors-users interlock 5. Need: Commitment to a yearly report of i. how EDA roadmap is used ii. by whom iii. feedback for improving it next year • 3
Are existing efforts OK (point to them as “meta-roadmap”) or not (new one needed) ?
Process for Today 1. Short (10-15 min) viewpoint talks in 20-min slots –
Leaving time for discussion
2. Different from last year: IP, IDM, foundry perspectives 3. Organizers will scribe discussion highlights and follow-up actions 4. Slides and discussion outcomes will be posted on the same website i. ii. iii. iv.
who is responsible for {development, review, integration} of roadmap? in what specific areas? (applications, embedded software, AMS, …) on what timeline? (when should we have follow-ups this year?) for what consumers? (ITRS Design/SysDrivers chapters, EDAC, …)
5. Misc: lunch signups, etc. 4
TECHNOLOGY GAPS IN EDA ROADMAP 1. End-product roadmaps (what is EDA enabling!?) x Semi companies compete on cost, TTM, quality
2. System-level - virtual platforms, executable specification TI, Bosch
3. Design space exploration – pathfinding (incl. 3D), IP selection, what-if analyses (incl. cost)* 4. SW synthesis and verification (concurrency) 5. Post-silicon: perf/power closure, diagnosis, debug * (Test?) 6. EDA scaling (cf. evolving computing platforms (manycore, accelerators, cloud) * Simply follow Moore’s Law, handle technology
7. Power management (analysis, optimization, power-driven design) * Apple, Google, Nokia
8. 3D (end of CMOS, heterogeneity, cost, perf, power) 9. Variability (trends), resilience, BTWC design? * 10. Analog / mixed-signal 11. Interoperability 5
NATURE OF EDA
1. Predictable (RAS?), incremental design flows (e.g., functional sim) 2. Wall time (tool, design process) 3. Hierarchy (passing design intent, integration) 4. IP encapsulation, migration, reuse 5. Extracting value from a mature technology node 6. Enabling user development? 7. Usability (product class-specific?)
8. Industry efficiency
6
ROADMAP = CHALLENGES + SOLUTIONS + METRICS
1. Standards (e.g., OpenPDK, IP encapsulation) 2. *Move from hardware to system (hw, sw, fw) level* = Expanding scope of EDA
3. Interoperability 4. *COST – of design, of product, of tool integration Design for Cost (what-if from spec to arch …)
5. Industry efficiency 6. Usability (e.g., enabling user development) Waves: long Tcl script foundation flows
7
NOTES 1. Other i. ii.
Business justification for EDA development Technology vs. design entitlement gap
2. What is the crisis? i.
According to what metric?
3. Sharing of EDA R&D / product metrics? 4. Verticalization of EDA?
8
ATTENDEES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.
David Kung, IBM
[email protected] Shishpal Rawat, Intel
[email protected] Nowjand Attaie, Intel
[email protected] Chin-Fu Chen, Qualcomm
[email protected] Myungsoo Jang, Samsung
[email protected] Woosick Choi, Hynix
[email protected] Walter Ng, GLOBALFOUNDRIES
[email protected] Nagaraj NS, TI
[email protected] James You, Broadcom
[email protected] Deepak Sherlekar, Virage Logic
[email protected] Yervant Zorian, Virage Logic
[email protected] Hisam El-Masry, CMC Microsystems
[email protected]
13. 14. 15. 16. 17.
Matthew Hogan, Mentor
[email protected] Roberto Suaya, Mentor
[email protected] Merlyn Brunken, Mentor
[email protected] Jay Adams, Synopsys
[email protected] Narendra Shenoy, Synopsys
[email protected]
18. 19. 20. 21. 22. 9 23.
William Joyner, SRC
[email protected] Sumit Dasgupta, Si2
[email protected] Ahmed Jerraya, CEA-LETI
[email protected] W. Rhett Davis, NC State Univ.
[email protected] Michael Kochte, Univ. Stuttgart
[email protected] Alper Sen, Bogazici Univ.
[email protected]