14:332:331 Computer Architecture and Assembly Language Spring 2006

Week 7 ALU Design

[Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides] 331 W07.1

Spring 2006

Head’s Up ‰

This week’s material z

MIPS logic and multiply instructions - Reading assignment – PH 3.1-3.4

z

MIPS ALU design - Reading assignment – PH B.5, B.6

331 W07.2

Spring 2006

Review: MIPS Arithmetic Instructions 31 R-type: I-Type: z

25

op

Rs

20

15

Rt

5

Rd

funct

0 A 32

zeroovf 1 1 ALU

op

Rs

Rt

Immed 16

expand immediates to 32 bits before ALU

z10

operations so can encode in 4 bits

B 32

32

4 m (operation)

0

add

Type

op

funct

1

addu

ADD

00

100000

2

sub

ADDU 00

100001

3

subu

SUB

00

100010

SUBU 00 AND

op

funct

4

and

100011

00

101000

5

or

00

100100

00

101001

6

xor

OR

00

100101

SLT

00

101010

7

nor

XOR

00

100110

SLTU 00

101011

a

slt

NOR

00

100111

00

101100

b

sltu

331 W07.3

Type

result

Spring 2006

Review: A 32-bit Adder/Subtractor Built out of 32 full adders (FAs)

B

1 bit FA

A0

1-bit FA c1

S0

A1

1-bit FA c2

S1

A2

1-bit FA c3

S2

B0

carry_in A

c0=carry_in

S

carry_out

B1

B2

...

‰

add/subt

S = A xor B xor carry_in

c31 carry_out = A∧B v A∧carry_in v B∧carry_in

A31

(majority function) B31 ‰

Small but slow!

331 W07.4

1-bit FA

S31

c32=carry_out Spring 2006

Minimal Implementation of a Full Adder ‰

Gate library: inverters, 2-input nands, or-and-inverters

architecture concurrent_behavior of full_adder is signal t1, t2, t3, t4, t5: std_logic; begin t1